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? 2003 microchip technology inc. preliminary ds30498b pic16f7x7 data sheet 28/40/44-pin, 8-bit cmos flash microcontrollers with 10-bit a/d and nanowatt technology www..net
ds30498b-page ii preliminary ? 2003 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semicondu ctor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving t he code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2003 microchip technology inc. preliminary ds30498b-page 1 pic16f7x7 low-power features: power managed modes: - primary run (xt, rc oscillator, 76 a, 1mhz, 2v) - rc_run (7 a, 31.25 khz, 2v) - sec_run (9 a, 32 khz, 2v) - sleep (0.1 a, 2v) timer1 oscillator (1.8 a, 32 khz, 2v) watchdog timer (0.7 a, 2v) two-speed oscillator start-up oscillators: three crystal modes: - lp, xt, hs (up to 20 mhz) two external rc modes one external clock mode: - ecio (up to 20 mhz) internal oscillator block: - 8 user-selectable frequencies (31 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4mhz, 8mhz) analog features: 10-bit, up to 14-channel analog-to-digital converter: - programmable acquisition time - conversion available during sleep mode dual analog comparators programmable low current brown-out reset (bor) circuitry and programmable low-voltage detect (lvd) peripheral features: high sink/source current: 25 ma two 8-bit timers with prescaler timer1/rtc module: - 16-bit timer/counter with prescaler - can be incremented during sleep via external 32 khz watch crystal master synchronous serial port (mssp) with 3-wire spi tm and i 2 c tm (master and slave) modes addressable universal synchronous asynchronous receiver transmitter (ausart) three capture, compare, pwm modules: - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10 bits parallel slave port (psp) ? 40/44-pin devices only special microcontroller features: fail-safe clock monitor for protecting critical applications against crystal failure two-speed start-up mode for immediate code execution power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) programmable code protection processor read access to program memory power saving sleep mode in-circuit serial programming ? (icsp ? ) via two pins mplab ? in-circuit debug (icd) via two pins mclr pin function replaceable with input only pin device program memory (# single-word instructions) data sram (bytes) i/o interrupts 10-bit a/d (ch) comparators ccp (pwm) mssp ausart timers 8/16-bit spi i 2 c (master) pic16f737 4096 368 25 16 11 2 3 yes yes yes 2/1 pic16f747 4096 368 36 17 14 2 3 yes yes yes 2/1 pic16f767 8192 368 25 16 11 2 3 yes yes yes 2/1 pic16f777 8192 368 36 17 14 2 3 yes yes yes 2/1 28/40/44-pin, 8-bit cmos fl ash microcontrollers with 10-bit a/d and nanowatt technology
pic16f7x7 ds30498b-page 2 preliminary ? 2003 microchip technology inc. pin diagrams pic16f737/767 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/lvdin/ss /c2out v ss osc2/clko/ra6 osc1/clki/ra7 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7/pgd rb6/pgc rb5/an13/ccp3 rb4/an11 rb3/ccp2 (1) /an9 rb2/an8 rb1/an10 rb0/int/an12 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda pdip, soic, ssop (28-pin) 2 3 4 5 6 1 7 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/lvdin/ss /c2out 15 16 17 18 19 20 21 rb0/int/an12 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda v ss osc2/clko/ra6 osc1/clki/ra7 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl 23 24 25 26 27 28 22 rb7/pgd rb6/pgc rb5/an13/ccp3 rb4/an11 rb3/ccp2 (1) /an9 rb2/an8 rb1/an10 10 11 8 912 13 14 qfn (28-pin) pic16f737 pic16f767 note 1: rb3 is the alternate pin for the ccp2 pin multiplexing. 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16f747 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 nc rb7/pgd rb6/pgc rb5/an13/ccp3 rb4/an11 rb3/ccp2 (1) /an9 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 rc0/t1oso/t1cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/lvdin/ss /c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int/an12 rb1/an10 rb2/an8 pic16f777 qfn (44-pin) v dd v ss nc
? 2003 microchip technology inc. preliminary ds30498b-page 3 pic16f7x7 pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16f747 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 nc rb7/pgd rb6/pgc rb5/an13/ccp3 rb4/an11 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc nc rc0/t1oso/t1cki osc1/clki/ra7 osc2/clko/ra6 v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/lvdin/ss /c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int/an12 rb1/an10 rb2/an8 rb3/ccp2 (1) /an9 tqfp (44-pin) pic16f777 rb7/pgd rb6/pgc rb5/an13/ccp3 rb4/an11 rb3/ccp2 (1) /an9 rb2/an8 rb1/an10 rb0/int/an12 v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/lvdin/ss /c2out re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc2/clko/ra6 osc1/clki/ra7 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16f747/777 pdip (40-pin) note 1: rb3 is the alternate pin for the ccp2 pin multiplexing.
pic16f7x7 ds30498b-page 4 preliminary ? 2003 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................ 5 2.0 memory organization......................................................................................................... ....................................................... 15 3.0 reading program memory...................................................................................................... .................................................. 31 4.0 oscillator configurations................................................................................................... ........................................................ 33 5.0 i/o ports................................................................................................................... ................................................................. 49 6.0 timer0 module ............................................................................................................... ........................................................... 73 7.0 timer1 module ............................................................................................................... ........................................................... 77 8.0 timer2 module ............................................................................................................... ........................................................... 85 9.0 capture/compare/pwm modules ................................................................................................. ............................................ 87 10.0 master synchronous serial port (mssp) module............................................................................... ...................................... 93 11.0 addressable universal synchronous asynchr onous receiver transmitter (usart) ................................................ ............ 133 12.0 analog-to-digital converter (a/d) module ................................................................................... ........................................... 151 13.0 comparator module .......................................................................................................... ...................................................... 161 14.0 comparator voltage reference module ........................................................................................ ......................................... 167 15.0 special features of the cpu ................................................................................................ .................................................. 169 16.0 instruction set summary.................................................................................................... ..................................................... 193 17.0 development support ........................................................................................................ ..................................................... 201 18.0 electrical characteristics................................................................................................. ........................................................ 207 19.0 dc and ac characteristics graphs and tables ................................................................................ ..................................... 237 20.0 packaging information ...................................................................................................... ...................................................... 239 appendix a: revision history ................................................................................................... ........................................................ 249 appendix b: device differences.................................................................................................. ...................................................... 249 appendix c: conversion considerations........................................................................................... ................................................ 250 index .......................................................................................................................... ........................................................................ 251 on-line support................................................................................................................ ................................................................ 259 systems information and upgrade hot line ....................................................................................... .............................................. 259 reader response ................................................................................................................ ............................................................. 260 pic16f7x7 product identification system ........................................................................................ ................................................ 261 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web 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? 2003 microchip technology inc. preliminary ds30498b-page 5 pic16f7x7 1.0 device overview this document contains device specific information about the following devices: pic16f737/767 devices are available only in 28-pin packages, while pic16f747/777 devices are available in 40-pin and 44-pin packages. all devices in the pic16f7x7 family share common architecture with the following differences: the pic16f737 and pic16f767 have one-half of the total on-chip memory of the pic16f747 and pic16f777. the 28-pin devices have 3 i/o ports, while the 40/44-pin devices have 5. the 28-pin devices have 16 interrupts, while the 40/44-pin devices have 17. the 28-pin devices have 11 a/d input channels, while the 40/44-pin devices have 14. the parallel slave port is implemented only on the 40/44-pin devices. low-power modes: rc_run allows the core and peripherals to be clocked from the intrc, while sec_run allows the core and peripherals to be clocked from the low-power timer1. refer to section 4.7 ?power managed modes? for further details. internal rc oscillator with eight selectable frequencies, including 31.25 khz, 125 khz, 250khz, 500khz, 1mhz , 2 mhz, 4 mhz and 8 mhz. the intrc can be configured as a primary or secondary clock source. refer to section 4.5 ?internal oscillator block? for further details. the timer1 module current consumption has been greatly reduced from 20 a (previous pic16 devices) to 1.8 a typical (32 khz at 2v), which is ideal for real-time clock applications. refer to section 7.0 ?timer1 module? for further details. extended watchdog timer (wdt) that can have a programmable period from 1 ms to 268s. the wdt has its own 16-bit prescaler. refer to section 15.17 ?watchdog timer (wdt)? for further details. two-speed start-up: when the oscillator is configured for lp, xt or hs, this feature will clock the device from the intrc while the oscillator is warming up. this, in turn, will enable almost immediate code execution. refer to section 15.17.3 ?two-speed clock start-up mode? for further details. fail-safe clock monitor: this feature will allow the device to continue operation if the primary or secondary clock source fails, by switching over to the intrc. the available features are summarized in table 1-1. block diagrams of the pic16f737/767 and pic16f747/777 devices are provided in figure 1-1 and figure 1-2, respectively. the pinouts for these device families are listed in table 1-2 and table 1-3. additional information may be found in the picmicro ? mid-range mcu family reference manual (ds33023), which may be obtained from your local microchip sales representative or downloaded from the microchip web site. the reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. table 1-1: pic16f7x7 device features pic16f737 pic16f767 pic16f747 pic16f777 key features pic16f737 pic16f747 pic16f767 pic16f777 operating frequency dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) flash program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 368 368 368 368 interrupts 16 17 16 17 i/o ports ports a, b, c ports a, b, c, d, e ports a, b, c ports a, b, c, d, e timers 3333 capture/compare/pwm modules 3 3 3 3 master serial communications mssp, usart mssp, usart mssp, usart mssp, usart parallel communications ? psp ? psp 10-bit analog-to-digital module 11 input channels 14 input channels 11 input channels 14 input channels instruction set 35 instructions 35 instructions 35 instructions 35 instructions packaging 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin qfn 44-pin tqfp 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin qfn 44-pin tqfp
pic16f7x7 ds30498b-page 6 preliminary ? 2003 microchip technology inc. figure 1-1: pic16f737 an d pic16f767 block diagram standard program memory 4k/8k x 14 13 data bus 8 14 program bus instruction register program counter 8-level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu wreg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko v dd , v ss porta portb portc porte ra4/t0cki/c1out ra5/an4/lvdin/ rb0/int/an12 rb7/pgd:rb6/pgc rc0/t1oso/t1cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt mclr /v pp /re3 8 8 brown-out reset note 1: pin location of ccp2 is determined by ccpmx in configuration word register 1. usart ccp1, 2, 3 mssp 10-bit a/d timer0 timer1 timer2 ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 8 3 bor/lvd addressable comparators flash rb1/an10 rb2/an8 rb3/ccp2 (1) /an9 rb4/an11 rb5/an13/ccp3 ss /c2out osc2/clko/ra6 osc1/clki/ra7 ra3/an3/v ref +
? 2003 microchip technology inc. preliminary ds30498b-page 7 pic16f7x7 figure 1-2: pic16f747 an d pic16f777 block diagram standard program memory 4k/8k x 14 13 data bus 8 14 program bus instruction register program counter 8-level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu wreg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko v dd , v ss porta portb portc portd porte ra4/t0cki/c1out ra5/an4/lvdin/ rc0/t1oso/t1cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt rd7/psp7:rd0/psp0 re0/rd /an5 re1/wr /an6 re2/cs /an7 8 8 brown-out reset note 1: pin location of ccp2 is determined by ccpmx in configuration word register 1. usart ccp1, 2, 3 mssp 10-bit a/d timer0 timer1 timer2 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 parallel slave port 8 3 comparators bor/lvd addressable rb0/int/an12 rb7/pgd:rb6/pgc rb1/an10 rb2/an8 rb3/ccp2 (1) /an9 rb4/an11 rb5/an13/ccp3 mclr/v pp /re3 flash ss /c2out osc2/clko/ra6 osc1/clki/ra7
pic16f7x7 ds30498b-page 8 preliminary ? 2003 microchip technology inc. table 1-2: pic16f737 and pic16f767 pinout description pin name pdip ssop soic pin # qfn pin # i/o/p type buffer type description osc1/clki/ra7 osc1 clki ra7 97 i i i/o st/cmos (3) st oscillator crystal or external clock input. oscillator crystal input or exte rnal clock source input. st buffer when configured in rc mode; otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). digital i/o. osc2/clko/ra6 osc2 clko ra6 10 6 o o i/o ? st oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. digital i/o. mclr /v pp /re3 mclr v pp re3 126 i p i st master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input only pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 227 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 328 i/o i ttl digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 41 i/o i i 0 ttl digital i/o. analog input 2. a/d reference voltage input (low). comparator voltage reference output. ra3/an3/v ref + ra3 an3 v ref + 52 i/o i i ttl digital i/o. analog input 3. a/d reference voltage input (high). ra4/t0cki/c1out ra4 t0cki c1out 63 i/o i o st digital i/o ? open-drain when configured as output. timer0 external clock input. comparator 1 output bit. ra5/an4/lvdin/ss /c2out ra5 an4 lvdin ss c2out 74 i/o i i/o i o ttl digital i/o. analog input 4. low-voltage detect input. spi slave select input. comparator 2 output bit. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. preliminary ds30498b-page 9 pic16f7x7 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int/an12 rb0 int an12 21 18 i/o i i ttl/st (1) digital i/o. external interrupt. analog input channel 12. rb1/an10 rb1 an10 22 19 i/o i ttl digital i/o. analog input channel 10. rb2/an8 rb2 an8 23 20 i/o i ttl digital i/o. analog input channel 8. rb3/ccp2/an9 rb3 ccp2 an9 24 21 i/o i/o i ttl digital i/o. ccp2 capture input, compare output, pwm output. analog input channel 9. rb4/an11 rb4 an11 25 22 i/o i ttl digital i/o. analog input channel 11. rb5/an13/ccp3 rb5 an13 ccp3 26 23 i/o i i/o ttl digital i/o. analog input channel 13. ccp3 capture input, compare output, pwm output. rb6/pgc rb6 pgc 27 24 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming clock. rb7/pgd rb7 pgd 28 25 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming data. table 1-2: pic16f737 and pic16f767 pinout description (continued) pin name pdip ssop soic pin # qfn pin # i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f7x7 ds30498b-page 10 preliminary ? 2003 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 8 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 12 9 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 13 10 i/o i/o st digital i/o. capture1 input, compare1 output, pwm1 output. rc3/sck/scl rc3 sck scl 14 11 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 15 12 i/o i i/o st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 13 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 14 i/o o i/o st digital i/o. usart asynchronous transmit. usart1 synchronous clock. rc7/rx/dt rc7 rx dt 18 15 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. v ss 8, 19 5, 16 p ? ground reference for logic and i/o pins. v dd 20 17 p ? positive supply for logic and i/o pins. table 1-2: pic16f737 and pic16f767 pinout description (continued) pin name pdip ssop soic pin # qfn pin # i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. preliminary ds30498b-page 11 pic16f7x7 table 1-3: pic16f747 and pic 16f777 pinout description pin name pdip pin # qfn pin # tqfp pin # i/o/p type buffer type description osc1/clki/ra7 osc1 clki ra7 13 32 31 i i i/o st/cmos (4) st oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). bidirectional i/o pin. osc2/clko/ra6 osc2 clko ra6 14 33 30 o o i/o ? st oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. bidirectional i/o pin. mclr /v pp /re3 mclr v pp re3 11818 i p i st master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active- low reset to the device. programming voltage input. digital input only pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 21919 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 32020 i/o i ttl digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 42121 i/o i i i ttl digital i/o. analog input 2. a/d reference voltage input (low). comparator voltage reference output. ra3/an3/v ref + ra3 an3 v ref + 52222 i/o i i ttl digital i/o. analog input 3. a/d reference voltage input (high). ra4/t0cki/c1out ra4 t0cki c1out 62323 i/o i o st digital i/o ? open-drain when configured as output. timer0 external clock input. comparator 1 output. ra5/an4/lvdin/ss /c2out ra5 an4 lvdin ss c2out 72424 i/o i i i i ttl digital i/o. analog input 4. low-voltage detect input. spi slave select input. comparator 2 output. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f7x7 ds30498b-page 12 preliminary ? 2003 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int/an12 rb0 int an12 33 9 8 i/o i i ttl/st (1) digital i/o. external interrupt. analog input channel 12. rb1/an10 rb1 an10 34 10 9 i/o i ttl digital i/o. analog input channel 10. rb2/an8 rb2 an8 35 11 10 i/o i ttl digital i/o. analog input channel 8. rb3/ccp2/an9 rb3 ccp2 an9 36 12 11 i/o i/o i ttl digital i/o. ccp2 capture input, compare output, pwm output. analog input channel 9. rb4/an11 rb4 an11 37 14 14 i/o i ttl digital i/o. analog input channel 11 rb5/an13/ccp3 rb5 an13 ccp3 38 15 15 i/o i i ttl digital i/o. analog input channel 13. ccp3 capture input, compare output, pwm output. rb6/pgc rb6 pgc 39 16 16 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming clock. rb7/pgd rb7 pgd 40 17 17 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming data. table 1-3: pic16f747 and pic16f777 pinout description (continued) pin name pdip pin # qfn pin # tqfp pin # i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. preliminary ds30498b-page 13 pic16f7x7 portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 15 34 32 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 16 35 35 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 17 36 36 i/o i/o st digital i/o. capture1 input, compare1 output, pwm1 output. rc3/sck/scl rc3 sck scl 18 37 37 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 23 42 42 i/o i i/o st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 24 43 43 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 44 44 i/o o i/o st digital i/o. usart asynchronous transmit. usart1 synchronous clock. rc7/rx/dt rc7 rx dt 26 1 1 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. table 1-3: pic16f747 and pic16f777 pinout description (continued) pin name pdip pin # qfn pin # tqfp pin # i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f7x7 ds30498b-page 14 preliminary ? 2003 microchip technology inc. portd is a bidirectional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 rd0 psp0 19 38 38 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 20 39 39 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 21 40 40 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 22 41 41 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 27 2 2 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd5/psp5 rd5 psp5 28 3 3 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd6/psp6 rd6 psp6 29 4 4 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd7/psp7 rd7 psp7 30 5 5 i/o i/o st/ttl (3) digital i/o. parallel slave port data. porte is a bidirectional i/o port. re0/rd /an5 re0 rd an5 82525 i/o i i st/ttl (3) digital i/o. read control for parallel slave port. analog input 5. re1/wr /an6 re1 wr an6 92626 i/o i i st/ttl (3) digital i/o. write control for parallel slave port. analog input 6. re2/cs /an7 re2 cs an7 10 27 27 i/o i i st/ttl (3) digital i/o. chip select control for parallel slave port. analog input 7. v ss ? 31 ? p ? analog ground reference. v ss 12, 31 6, 30 6, 29 p ? ground reference for logic and i/o pins. v dd ? 8 ? p ? analog positive supply. v dd 11, 32 7, 28 7, 28 p ? positive supply for logic and i/o pins. nc ? 13, 29 12, 13, 33, 34 ? ? these pins are not internally connected. these pins should be left unconnected. table 1-3: pic16f747 and pic16f777 pinout description (continued) pin name pdip pin # qfn pin # tqfp pin # i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. preliminary ds30498b-page 15 pic16f7x7 2.0 memory organization there are two memory blocks in each of these picmicro ? mcus. the program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. the program memory can be read internally by user code (see section 3.0 ?reading program memory? ). additional information on device memory may be found in the picmicro ? mid-range mcu family reference manual (ds33023). 2.1 program memory organization the pic16f7x7 devices have a 13-bit program counter capable of addressing an 8k word x 14-bit program memory space. the pic16f767/777 devices have 8k words of flash program memory and the pic16f737/747 devices have 4k words. the program memory maps for pic16f7x7 devices are shown in figure 2-1. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits: each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file (shown in figure 2-2 and figure 2-3) can be accessed either directly, or indirectly, through the file select register (fsr). figure 2-1: program memory maps and stacks for pic16f7x7 devices rp1:rp0 bank 00 0 01 1 10 2 11 3 pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 0fffh 1000h 07ffh 0800h page 1 17ffh 1800h page2 page 3 memory available on all pic16f7x7. memory available on pic16f767 and pic16f777. the memory wraps to 000h through 0fffh on the pic16f737 and pic16f747.
pic16f7x7 ds30498b-page 16 preliminary ? 2003 microchip technology inc. figure 2-2: data memory map fo r pic16f737 and the pic16f767 indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 option_reg pcl status fsr trisa trisb pclath intcon pie1 pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations read as ? 0 ?. * not a physical register. file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh indirect addr. (*) tmr0 option_reg pir2 pie2 adresh adcon0 adcon1 general purpose register accesses 70h-7fh trisb portb 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h pmdata pmadr pmcon1 pmdath pmadrh 17fh 1ffh bank 2 bank 3 19fh 1a0h 11fh 120h cvrcon osccon cmcon adresl tmr1l tmr1h t1con tmr2 ccpr1l ccpr1h ccp1con rcsta txreg rcreg pr2 txsta spbrg t2con osctune wdtcon efh f0h general purpose register 80 bytes 16fh 170h general purpose register 80 bytes 1efh 1f0h general purpose register 80 bytes general purpose register 16 bytes general purpose register 16 bytes accesses 70h-7fh accesses 70h-7fh sspbuf sspcon sspadd sspstat adcon2 portc porte trisc trise ccpr2l ccpr2h ccp2con sspcon2 ccpr3l ccpr3h ccp3con lvdcon file address file address file address
? 2003 microchip technology inc. preliminary ds30498b-page 17 pic16f7x7 figure 2-3: data memory map for pic16f747 and the pic16f777 indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 option_reg pcl status fsr trisa trisb pclath intcon pie1 pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations read as ? 0 ?. * not a physical register. file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh indirect addr. (*) tmr0 option_reg pir2 pie2 adresh adcon0 adcon1 general purpose register accesses 70h-7fh trisb portb 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h pmdata pmadr pmcon1 pmdath pmadrh 17fh 1ffh bank 2 bank 3 19fh 1a0h 11fh 120h cvrcon osccon cmcon adresl tmr1l tmr1h t1con tmr2 ccpr1l ccpr1h ccp1con rcsta txreg rcreg pr2 txsta spbrg t2con osctune wdtcon efh f0h general purpose register 80 bytes 16fh 170h general purpose register 80 bytes 1efh 1f0h general purpose register 80 bytes general purpose register 16 bytes general purpose register 16 bytes accesses 70h-7fh accesses 70h-7fh sspbuf sspcon sspadd sspstat adcon2 portc porte trisc trise ccpr2l ccpr2h ccp2con sspcon2 portd trisd ccpr3l ccpr3h ccp3con lvdcon file address file address file address
pic16f7x7 ds30498b-page 18 preliminary ? 2003 microchip technology inc. 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page bank 0 00h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 30, 180 01h tmr0 timer0 module register xxxx xxxx 76, 180 02h (4) pcl program counter (pc) least significant byte 0000 0000 29, 180 03h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 21, 180 04h (4) fsr indirect data memory address pointer xxxx xxxx 30, 180 05h porta porta data latch when written: porta pins when read xx0x 0000 55, 180 06h portb portb data latch when written: portb pins when read xx00 0000 64, 180 07h portc portc data latch when written: portc pins when read xxxx xxxx 66, 180 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx 67, 180 09h (5) porte ? ? ? ? re3 re2 re1 re0 ---- x000 68, 180 0ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 29, 180 0bh (4) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 23, 180 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 25, 180 0dh pir2 osfif cmif lvdif ?bclif ? ccp3if ccp2if 000- 0-00 27, 180 0eh tmr1l holding register for the least signi ficant byte of the 16-bit tmr1 register xxxx xxxx 83, 180 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 83, 180 10h t1con ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 83, 180 11h tmr2 timer2 module register 0000 0000 86, 180 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 86, 180 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx 101, 180 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 101, 180 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx 90, 180 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx 90, 180 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 88, 180 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 134, 180 19h txreg usart transmit data register 0000 0000 139, 180 1ah rcreg usart receive data register 0000 0000 141, 180 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx 92, 180 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx 92, 180 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 88, 180 1eh adresh a/d result register byte xxxx xxxx 160, 180 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 152, 180 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessib le. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices (except for re3), read as ? 0 ?. 6: this bit always reads as a ? 1 ?. 7: oscon bit resets to ? 0 ? with dual-speed start-up and lp, hs or hs-pll selected as the oscillator. 8: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 19 pic16f7x7 bank 1 80h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 30, 180 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 22, 180 82h (4) pcl program counter?s (pc) least significant byte 0000 0000 29, 180 83h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 21, 180 84h (4) fsr indirect data memory address pointer xxxx xxxx 30, 180 85h trisa porta data direction register 1111 1111 55, 181 86h trisb portb data direction register 1111 1111 64, 181 87h trisc portc data direction register 1111 1111 66, 181 88h (5) trisd portd data direction register 1111 1111 67, 181 89h (5) trise ibf (5) obf (5) ibov (5) pspmode (5) ? (8) porte data direction bits 0000 1111 69, 181 8ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23, 180 8bh (4) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 25, 180 8ch pie1 pspie (3) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 24, 181 8dh pie2 osfie cmie lvdie ?bclie ? ccp3ie ccp2ie 000- 0-00 26, 181 8eh pcon ? ? ? ? ? sboren por bor ---- -1qq 28, 181 8fh osccon ? ircf2 ircf1 ircf0 osts (8) iofs scs1 scs0 -000 1000 38, 181 90h osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 36, 181 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 105 92h pr2 timer2 period register 1111 1111 86, 181 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 101, 181 94h sspstat smp cke d/a psr/w ua bf 0000 0000 101, 181 95h ccpr3l capture/compare/pwm register 1 (lsb) xxxx xxxx 92 96h ccpr3h capture/compare/pwm register 1 (msb) xxxx xxxx 92 97h ccp3con ? ? ccp3x ccp3y ccp3m3 ccp3m2 ccp3m1 ccp3m0 --00 0000 92 98h txsta csrc tx9 txen sync ?brghtrmttx9d 0000 -010 145, 181 99h spbrg baud rate generator register 0000 0000 145, 181 9ah ? unimplemented ? ? 9bh adcon2 ? ?acqt2acqt1acqt0 ? ? ? --00 0--- 154 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 55, 161 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 55, 167 9eh adresl a/d result register low byte xxxx xxxx 180 9fh adcon1 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 153, 181 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessib le. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices (except for re3), read as ? 0 ?. 6: this bit always reads as a ? 1 ?. 7: oscon bit resets to ? 0 ? with dual-speed start-up and lp, hs or hs-pll selected as the oscillator. 8: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
pic16f7x7 ds30498b-page 20 preliminary ? 2003 microchip technology inc. bank 2 100h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 30, 180 101h tmr0 timer0 module register xxxx xxxx 76, 180 102h (4) pcl program counter (pc) least significant byte 0000 0000 29, 180 103h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 21, 180 104h (4) fsr indirect data memory address pointer xxxx xxxx 30, 180 105h wdtcon ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten ---0 1000 187 106h portb portb data latch when written: portb pins when read xxxx xxxx 64, 180 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 176 10ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23, 180 10bh (4) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 25, 180 10ch pmdata eeprom data register low byte xxxx xxxx 32, 181 10dh pmadr eeprom address register low byte xxxx xxxx 32, 181 10eh pmdath ? ? eeprom data register high byte --xx xxxx 32, 181 10fh pmadrh ? ? ? ? eeprom address register high byte ---- xxxx 32, 181 bank 3 180h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 30, 180 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 22, 180 182h (4) pcl program counter (pc) least significant byte 0000 0000 29, 180 183h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 21, 180 184h (4) fsr indirect data memory address pointer xxxx xxxx 30, 180 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 64, 181 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,4) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 23, 180 18bh (4) intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 25, 180 18ch pmcon1 ? ? ? ? ? ? ?rd ---- ---0 32, 181 18dh ? reserved, maintain clear 0000 0000 ? 18eh ? reserved, maintain clear 0000 0000 ? 18fh ? reserved, maintain clear 0000 0000 ? table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessib le. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter during branches ( call or goto ). 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear. 4: these registers can be addressed from any bank. 5: portd, porte, trisd and trise are not physically implemented on the 28-pin devices (except for re3), read as ? 0 ?. 6: this bit always reads as a ? 1 ?. 7: oscon bit resets to ? 0 ? with dual-speed start-up and lp, hs or hs-pll selected as the oscillator. 8: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 21 pic16f7x7 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status reg- ister is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is dis- abled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable, therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status , will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see section 16.0 ?instruction set summary? . register 2-1: status register (address 03h, 83h, 103h, 183h) note 1: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h-1ffh) 0 = bank 0, 1 (00h-ffh) bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h-1ffh) 10 = bank 2 (100h-17fh) 01 = bank 1 (80h-ffh) 00 = bank 0 (00h-7fh) each bank is 128 bytes. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw, sublw, subwf instructions) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf, addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 22 preliminary ? 2003 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readable and writable register which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option_reg register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2003 microchip technology inc. preliminary ds30498b-page 23 pic16f7x7 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 int0ie : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 24 preliminary ? 2003 microchip technology inc. 2.2.2.4 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt note 1: pspie is reserved on 28-pin devices; always maintain this bit clear. bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 25 pic16f7x7 2.2.2.5 pir1 register the pir1 register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1 register (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred note: pspif is reserved on 28-pin devices; always maintain this bit clear. bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion is completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty 0 = the usart transmit buffer is full bit 3 sspif : synchronous serial port (ssp) interrupt flag bit 1 = the ssp interrupt condition has occurred and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi: a transmission/reception has taken place. i 2 c slave: a transmission/reception has taken place. i 2 c master: a transmission/reception has taken place. the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multi-master system). a stop condition occurred while the ssp module was idle (multi-master system). 0 = no ssp interrupt condition has occurred bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 26 preliminary ? 2003 microchip technology inc. 2.2.2.6 pie2 register the pie2 register contains the individual enable bits for the ccp2 and ccp3 peripheral interrupts. register 2-6: pie2 register (address 8dh) r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 osfie cmie lvdie ?bclie ? ccp3ie ccp2ie bit 7 bit 0 bit 7 osfie: oscillator fail interrupt enable bit 1 = enabled 0 = disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 = disabled bit 5 lvdie: low-voltage detect interrupt enable bit 1 = lvd interrupt is enabled 0 = lvd interrupt is disabled bit 4 unimplemented: read as ? 0 ? bit 3 bclie: bus collision interrupt enable bit 1 = enable bus collision interrupt in the ssp when configured for i 2 c master mode 0 = disable bus collision interrupt in the ssp when configured for i 2 c master mode bit 2 unimplemented: read as ? 0 ? bit 1 ccp3ie: ccp3 interrupt enable bit 1 = enables the ccp3 interrupt 0 = disables the ccp3 interrupt bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 27 pic16f7x7 2.2.2.7 pir2 register the pir2 register contains the flag bits for the ccp2 interrupt. register 2-7: pir2 register (address 0dh) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 osfif cmif lvdif ?bclif ? ccp3if ccp2if bit 7 bit 0 bit 7 osfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intrc (must be cleared in software) 0 = system clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5 lvdif: low-voltage detect interrupt flag bit 1 = the supply voltage has fallen below the specified lvd voltage (must be cleared in software) 0 = the supply voltage is greater then the specified lvd voltage bit 4 unimplemented: read as ? 0 ? bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision has occurred in the ssp when configured for i 2 c master mode 0 = no bus collision has occurred bit 2 unimplemented: read as ? 0 ? bit 1 ccp3if: ccp3 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 0 ccp2if : ccp2 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 28 preliminary ? 2003 microchip technology inc. 2.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. register 2-8: pcon register (address 8eh) note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is not predictable if the brown-out circuit is disabled (by clearing the boren bit in the configuration word register). u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-1 ? ? ? ? ? sboren por bor bit 7 bit 0 bit 7-3 unimplemented: read as ? 0 ? bit 2 sboren : software brown-out reset enable bit if borsen in configuration word 2 is a ? 1 ? and boren in configuration word 1 is ? 0 ?, then: 1 = bor enabled 0 = bor disabled bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 29 pic16f7x7 2.3 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-4 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-4: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note, an556, ?implementing a table read? (ds00556). 2.3.2 stack the pic16f7x7 family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging pic16f7x7 devices are capable of addressing a con- tinuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is poped off the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions or the vectoring to an interrupt address. note: the contents of the pclath are unchanged after a return or retfie instruction is executed. the user must set up the pclath for any subsequent call s or goto s. org 0x500 bcf pclath, 4 bsf pclath, 3 ;select page 1 ;(800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine : ;page 1 (800h-fffh) : return ;return to call ;subroutine in page 0 ;(000h-7ffh)
pic16f7x7 ds30498b-page 30 preliminary ? 2003 microchip technology inc. 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actu- ally accesses the register pointed to by the file select register, fsr. reading the indf register itself indi- rectly (fsr = 0 ) will read 00h. writing to the indf reg- ister indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>) as shown in figure 2-5. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing figure 2-5: direct/indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr, f ;inc pointer btfss fsr, 4 ;all done? goto next ;no clear next continue : ;yes continue note 1: for register file map detail, see figure 2-2. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
? 2003 microchip technology inc. preliminary ds30498b-page 31 pic16f7x7 3.0 reading pr ogram memory the flash program memory is readable during normal operation over the entire v dd range. it is indirectly addressed through special function registers (sfr). up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ascii, etc. executing a program memory location con- taining data that forms an invalid instruction results in a nop . there are five sfrs used to read the program and memory. these registers are: pmcon1 pmdata pmdath pmadr pmadrh the program memory allows word reads. program memory access allows for checksum calculation and reading calibration tables. when interfacing to the program memory block, the pmdath:pmdata registers form a two-byte word which holds the 14-bit data for reads. the pmadrh:pmadr registers form a two-byte word which holds the 13-bit address of the flash location being accessed. these devices can have up to 8k words of program flash, with an address range from 0h to 3fffh. the unused upper bits in both the pmdath and pmadrh registers are not implemented and read as ? 0 ?s. 3.1 pmadr the address registers can address up to a maximum of 8k words of program flash. when selecting a program address value, the msbyte of the address is written to the pmadrh register and the lsbyte is written to the pmadr register. the upper msbits of pmadrh must always be clear. 3.2 pmcon1 register pmcon1 is the control register for memory accesses. the control bit, rd, initiates read operations. this bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the read operation. register 3-1: pmcon1 register (address 18ch) r-1 u-0 u-0 u-0 u-x u-0 u-0 r/s-0 reserved ? ? ? ? ? ?rd bit 7 bit 0 bit 7 reserved: read as ? 1 ? bit 6-1 unimplemented : read as ? 0 ? bit 0 rd : read control bit 1 = initiates a flash read, rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = flash read completed legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 32 preliminary ? 2003 microchip technology inc. 3.3 reading the flash program memory a program memory location may be read by writing two bytes of the address to the pmadr and pmadrh reg- isters and then setting control bit, rd (pmcon1<0>). once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. the data is available in the pmdata and pmdath regis- ters after the second nop instruction. therefore, it can be read as two bytes in the following instructions. the pmdata and pmdath registers will hold this value until the next read operation. 3.4 operation during code-protect flash program memory has its own code-protect mechanism. external read and write operations by programmers are disabled if this mechanism is enabled. the microcontroller can read and execute instructions out of the internal flash program memory, regardless of the state of the code-protect configuration bits. example 3-1: flash program read table 3-1: registers associated with program flash bsf status, rp1 ; bcf status, rp0 ; bank 2 movf addrh, w ; movwf pmadrh ; msbyte of program address to read movf addrl, w ; movwf pmadr ; lsbyte of program address to read bsf status, rp0 ; bank 3 required required bsf pmcon1, rd ; eeprom read sequence sequence nop ; memory is read in the next two cycles after bsf pmcon1,rd nop ; bcf status, rp0 ; bank 2 movf pmdata, w ; w = lsbyte of program pmdata movf pmdath, w ; w = msbyte of program pmdath address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 10dh pmadr address register low byte xxxx xxxx uuuu uuuu 10fh pmadrh ? ? ? address register high byte ---x xxxx ---u uuuu 10ch pmdata data register low byte xxxx xxxx uuuu uuuu 10eh pmdath ? ? data register high byte --xx xxxx --uu uuuu 18ch pmcon1 ? (1) ? ? ? ? ? ? rd 1--- ---0 1--- ---0 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ? 0 ?. shaded cells are not used during flash access. note 1: this bit always reads as a ? 1 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 33 pic16f7x7 4.0 oscillator configurations 4.1 oscillator types the pic16f7x7 can be operated in eight different oscil- lator modes. the user can pr ogram three configuration bits (f osc 2:f osc 0) to select one of these eight modes (modes 5-8 are new pic16 oscillator configurations): 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. rc external resistor/capacitor with f osc /4 output on ra6 5. rcio external resistor/capacitor with i/o on ra6 6. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 7. intio2 internal oscillator with i/o on ra6 and ra7 8. ecio external clock with i/o on ra6 4.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clki and osc2/clko pins to establish oscillation (see figure 4-1 and figure 4-2). the pic16f7x7 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturer?s specifications. figure 4-1: crystal operation (hs, xt or lp osc configuration) table 4-1: capacitor selection for crystal oscillator (for design guidance only) note 1: see table 4-1 for typical values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen (typically between 2 m ? to 10 m ?) . c1 (1) c2 (1) xtal osc2 r s (2) osc1 r f (3) sleep to internal logic pic16f7x7 osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 56 pf 56 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15 pf 15 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each crystal has its own character- istics, the user should consult the crystal manufacturer for appropriate values of external components. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application.
pic16f7x7 ds30498b-page 34 preliminary ? 2003 microchip technology inc. figure 4-2: ceramic resonator operation (hs or xt osc configuration) table 4-2: ceramic resonators (for design guidance only) 4.3 external clock input the ecio oscillator mode requires an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ecio oscillator mode, the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 4-3 shows the pin connections for the ecio oscillator mode. figure 4-3: external clock input operation (ecio configuration) typical capacitor values used: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. note: when using resonators with frequencies above 3.5 mhz, the use of hs mode rather than xt mode is recommended. hs mode may be used at any v dd for which the controller is rated. if hs is selected, it is possible that the gain of the oscillator will overdrive the resonator. therefore, a series resistor should be placed between the osc2 pin and the resonator. as a good starting point, the recommended value of r s is 330 ?. note 1: see table 4-2 for typical values of c1 and c2. 2: a series resistor (r s ) may be required. 3: r f varies with the resonator chosen (typically between 2 m ? to 10 m ?) . c1 (1) c2 (1) res osc2 r s (2) osc1 r f (3) sleep to internal logic pic16f7x7 osc1/clki i/o (osc2) ra6 clock from ext. system pic16f7x7
? 2003 microchip technology inc. preliminary ds30498b-page 35 pic16f7x7 4.4 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal man- ufacturing variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account varia- tion due to tolerance of external r and c components used. figure 4-4 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 4-4: rc oscillator mode the rcio oscillator mode (figure 4-5) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 4-5: rcio oscillator mode 4.5 internal oscillator block the pic16f7x7 devices include an internal oscillator block which generates two different clock signals; either can be used as the system?s clock source. this can eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source which can be used to directly drive the system clock. it also drives the intosc postscaler which can provide a range of six clock frequencies, from 125 khz to 4 mhz. the other clock source is the internal rc oscillator (intrc), which provides a 31.25 khz (32 s nominal period) output. the intrc oscillator is enabled by selecting the intrc as the system clock source or when any of the following are enabled: power-up timer watchdog timer two-speed start-up fail-safe clock monitor these features are discussed in greater detail in section 15.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct or intosc postscaler) is selected by configuring the ircf bits of the osccon register (page 38). osc2/clko c ext r ext pic16f7x7 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf c ext r ext pic16f7x7 osc1 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf i/o (osc2) ra6 note: throughout this data sheet, when referring specifically to a generic clock source, the term ?intrc? may also be used to refer to the clock modes using the internal oscillator block. this is regardless of whether the actual frequency used is intosc (8 mhz), the intosc postscaler or intrc (31.25 khz).
pic16f7x7 ds30498b-page 36 preliminary ? 2003 microchip technology inc. 4.5.1 intrc modes using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. 4.5.2 osctune register the internal oscillator?s output has been calibrated at the factory but can be adjusted in the application. this is done by writing to the osctune register (register 4-1). the tuning sensitivity is constant throughout the tuning range. the osctune register has a tuning range of 12.5%. when the osctune register is modified, the intosc and intrc frequencies will begin shifting to the new fre- quency. the intrc clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s); the intosc clock will stabilize within 1 ms. code execu- tion continues during this shift. there is no indication that the shift has occurred. operation of features that depend on the 31.25 khz intrc clock source frequency, such as the wdt, fail-safe clock monitor and peripherals, will also be affected by the change in frequency. register 4-1: osctune: oscillator tuning register (address 90h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frequency tuning bits 011111 = maximum frequency 011110 = 000001 = 000000 = center frequency. oscillator module is running at the calibrated frequency. 111111 = 100000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 37 pic16f7x7 4.6 clock sources and oscillator switching the pic16f7x7 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. pic16f7x7 devices offer three alternate clock sources. when enabled, these give additional options for switching to the various power managed operating modes. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block (intrc) the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock mode and the internal oscillator block. the particular mode is defined on por by the contents of configuration word 1. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power managed mode. pic16f7x7 devices offer the timer1 oscillator as a secondary oscillator. this oscillator continues to run when a sleep instruction is executed and is often the time base for functions, such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rc0/t1oso/t1cki and rc1/t1osi/ccp2 pins. like the lp mode oscillator circuit, loading capaci- tors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 7.6 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. the 31.25 khz intrc source is also used as the clock source for several special fea- tures, such as the wdt, fail-safe clock monitor, power-up timer and two-speed start-up. the clock sources for the pic16f7x7 devices are shown in figure 4-6. see section 7.0 ?timer1 module? for fur- ther details of the timer1 oscillator. see section 15.1 ?configuration bits? for configuration register details. 4.6.1 osccon register the osccon register (register 4-2) controls several aspects of the system clock?s operation, both in full power operation and in power managed modes. the system clock select bits, scs1:scs0, select the clock source that is used when the device is operating in power managed modes. when the bits are cleared (scs<1:0> = 00 ), the system clock source comes from the main oscillator that is selected by the f osc 2:f osc 0 configuration bits in configuration register 1. when the bits are set in any other manner, the system clock source is provided by the timer1 oscillator (scs1:scs0 = 01 ) or from the internal oscillator block (scs1:scs0 = 10 ). after a reset, scs<1:0> are always set to ? 00 ?. the internal oscillator select bits, ircf2:ircf0, select the frequency output of the internal oscillator block that is used to drive the system clock. the choices are the intrc source (31.25 khz), the intosc source (8 mhz) or one of the six frequencies derived from the intosc postscaler (125 khz to 4 mhz). changing the configuration of these bits has an immediate change on the internal oscillator?s output. the osts and iofs bits indicate the status of the primary oscillator and intosc source; these bits are set when their respective oscillators are stable. in par- ticular, osts indicates that the oscillator start-up timer has timed out. 4.6.2 clock switching clock switching will occur for the following reasons: the fcmen (config2<0>) bit is set, the device is running from the primary oscillator and the primary oscillator fails. the clock source will be 31.25 khz intrc. the fcmen bit is set, the device is running from the t1osc and t1osc fails. the clock source will be 31.25 khz intrc. following a wake-up due to a reset or a por, when the device is configured for two-speed mode, switching will occur between the intrc and the system clock defined by the f osc <2:0> bits. a wake-up from sleep occurs due to interrupt or wdt wake-up and two-speed start-up is enabled. if the primary clock is xt, hs or lp, the clock will switch between the intrc and the primary system clock after 1024 clocks (ost) and 8 clocks of the primary oscillator. this is conditional upon the scs bits being set equal to ? 00 ?. scs bits are modified from their original value. ircf bits are modified from their original value. note: because the scs bits are cleared on any reset, no clock switching will occur on a reset unless the two-speed start-up is enabled and the primary clock is xt, hs or lp. the device will wait for the primary clock to become stable before execution begins (two-speed start-up disabled).
pic16f7x7 ds30498b-page 38 preliminary ? 2003 microchip technology inc. 4.6.3 clock transition and wdt when clock switching is performed, the watchdog timer is disabled because the watchdog ripple counter is used as the oscillator start-up timer. once the clock transition is complete (i.e., new oscilla- tor selection switch has occurred), the watchdog counter is re-enabled with the counter reset. this allows the user to synchronize the watchdog timer to the start of execution at the new clock frequency. register 4-2: osccon: oscillator cont rol register note: the ost is only used when switching to xt, hs and lp oscillator modes. u-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 ? ircf2 ircf1 ircf0 osts (1) iofs scs1 scs0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-4 ircf<2:0>: internal rc oscillator frequency select bits 000 = 31.25 khz 001 = 125 khz 010 = 250 khz 011 = 500 khz 100 = 1 mhz 101 = 2 mhz 110 = 4 mhz 111 = 8 mhz bit 3 osts: oscillator start-up time-out status bit (1) 1 = device is running from the primary system clock 0 = device is running from t1osc or intrc as a secondary system clock note 1: bit resets to ? 0 ? with two-speed start-up and lp, xt or hs selected as the oscillator mode. bit 2 iofs: intosc frequency stable bit 1 = frequency is stable 0 = frequency is not stable bit 1-0 scs<1:0>: oscillator mode select bits 00 = oscillator mode defined by f osc <2:0> 01 = t1osc is used for system clock 10 = internal rc is used for system clock 11 = reserved legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 39 pic16f7x7 figure 4-6: pic16f7x7 clock diagram 4.6.4 modifying the ircf bits the ircf bits can be modified at any time, regardless of which clock source is currently being used as the system clock. the internal oscillator allows users to change the frequency during run-time. this is achieved by modifying the ircf bits in the osccon register. the sequence of events that occur after the ircf bits are modified is dependent upon the initial value of the ircf bits before they are modified. if the intrc (31.25 khz, ircf<2:0> = 000 ) is running and the ircf bits are modified to any other value than ? 000 ?, a 4 ms clock switch delay is turned on. code execution contin- ues at a higher than expected frequency while the new frequency stabilizes. time sensitive code should wait for the iofs bit in the osccon register to become set before continuing. this bit can be monitored to ensure that the frequency is stable before using the system clock in time critical applications. if the ircf bits are modified while the internal oscillator is running at any other frequency than intrc (31.25 khz, ircf<2:0> 000 ), there is no need for a 4 ms clock switch delay. the new intosc frequency will be stable immediately after the eight falling edges. the iofs bit will remain set after clock switching occurs. secondary oscillator t1oscen enable oscillator t1oso t1osi osc1 osc2 sleep primary oscillator lp, xt, hs, rc, ec t1osc cpu peripherals postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31.25 khz 31.25 khz source internal oscillator block wdt, fscm 31.25 khz 8 mhz internal oscillator (intrc) (intosc) config1 (f osc 2:f osc 0) scs<1:0> (t1osc) to ti m e r 1 note: caution must be taken when modifying the ircf bits using bcf or bsf instructions. it is possible to modify the ircf bits to a fre- quency that may be out of the v dd specifi- cation range; for example, v dd = 2.0v and ircf = 111 (8 mhz).
pic16f7x7 ds30498b-page 40 preliminary ? 2003 microchip technology inc. 4.6.5 clock transition sequence the following are three different sequences for switching the internal rc oscillator frequency: clock before switch: 31.25 khz (ircf<2:0> = 000 ) 1. ircf bits are modified to an intosc/intosc postscaler frequency. 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. the iofs bit is clear to indicate that the clock is unstable and a 4 ms delay is started. time dependent code should wait for iofs to become set. 5. switchover is complete. clock before switch: one of intosc/intosc postscaler (ircf<2:0> 000 ) 1. ircf bits are modified to intrc (ircf<2:0> = 000 ). 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. oscillator switchover is complete. clock before switch: one of intosc/intosc postscaler (ircf<2:0> 000 ) 1. ircf bits are modified to a different intosc/ intosc postscaler frequency. 2. the clock switching circuitry waits for a falling edge of the current clock, at which point clko is held low. 3. the clock switching circuitry then waits for eight falling edges of requested clock, after which it switches clko to this new clock source. 4. the iofs bit is set. 5. oscillator switchover is complete. 4.6.6 oscillator delay upon power-up, wake-up and clock switching table 4-3 shows the different delays invoked for various clock switching sequences. it also shows the delays invoked for por and wake-up. table 4-3: oscillator delay examples switch from switch to frequency oscillator delay comments sleep/por intrc t1osc intosc/intosc postscaler 31.25 khz 32.768 khz 125 khz-8 mhz 5 s-10 s (approx.) cpu start-up (1) following a wake-up from sleep mode or por, cpu start-up is invoked to allow the cpu to become ready for code execution. intrc/sleep ec, rc dc ? 20 mhz intrc (31.25 khz) ec, rc dc ? 20 mhz sleep lp, xt, hs 32.768 khz-20 mhz 1024 clock cycles (ost) following a change from intrc, an ost of 1024 cycles must occur. intrc (31.25 khz) intosc/intosc postscaler 125 khz-8 mhz 4 ms refer to section 4.6.4 ?modifying the ircf bits? for further details. note 1: the 5 s-10 s start-up delay is based on a 1 mhz system clock.
? 2003 microchip technology inc. preliminary ds30498b-page 41 pic16f7x7 4.7 power managed modes 4.7.1 rc_run mode when scs bits are configured to run from the intrc, a clock transition is generated if the system clock is not already using the intrc. the event will clear the osts bit and switch the system clock from the primary system clock (if scs<1:0> = 00 ) determined by the value contained in the configuration bits, or from the t1osc (if scs<1:0> = 01 ) to the intrc clock option, and shut down the primary system clock to conserve power. clock switching will not occur if the primary system clock is already configured as intrc. if the system clock does not come from the intrc (31.25 khz) when the scs bits are changed and the ircf bits in the osccon register are configured for a frequency other than intrc, the frequency may not be stable immediately. the iofs bit (osccon<2> will be set when the intosc or postscaler frequency is stable, after approximately 4 ms. after a clock switch has been executed, the osts bit is cleared, indicating a low-power mode and the device does not run from the primary system clock. the inter- nal q clocks are held in the q1 state until eight falling edge clocks are counted on the intrc oscillator. after the eight clock periods have transpired, the clock input to the q clocks is released and operation resumes (see figure 4-7). figure 4-7: timing diagram for xt , hs, lp, ec, extrc to rc_run mode q4 q3 q2 osc1 scs<1:0> program pc + 1 pc note 1: t inp = 32 s typical. 2: t osc = 50 ns minimum. 3: t scs = 8 t inp . 4: t dly = 1 t inp . q1 intosc q1 t scs (3) counter q1 t inp (1) system clock t osc (2) q3 q2 q4 q1 q2 pc + 2 pc + 3 q3 q4 q1 t dly (4)
pic16f7x7 ds30498b-page 42 preliminary ? 2003 microchip technology inc. 4.7.2 sec_run mode the core and peripherals can be configured to be clocked by t1osc using a 32.768 khz crystal. the crystal must be connected to the t1oso and t1osi pins. this is the same configuration as the low-power timer circuit (see section 7.6 ?timer1 oscillator? ). when scs bits are configured to run from t1osc, a clock transition is generated. it will clear the osts bit, switch the system clock from either the primary system clock or intrc, depending on the value of scs<1:0> and f osc <2:0>, to the external low-power timer1 oscillator input (t1osc) and shut down the primary system clock to conserve power. after a clock switch has been executed, the internal q clocks are held in the q1 state until eight falling edge clocks are counted on the t1osc. after the eight clock periods have transpired, the clock input to the q clocks is released and operation resumes (see figure 4-8). in addition, t1run (in t1con) is set to indicate that t1osc is being used as the system clock. figure 4-8: timing diagram fo r switching to sec_run mode note 1: the t1oscen bit must be enabled and it is the user?s responsibility to ensure t1osc is stable before clock switching to the t1osc input clock can occur. 2: when t1oscen = 0 , the following possible effects result. original scs<1:0> modified scs<1:0> final scs<1:0> 00 01 00 ? no change 00 11 10 ? intrc 10 11 10 ? no change 10 01 00 ? osc defined by f osc <2:0> a clock switching event will occur if the final state of the scs bits is different from the original. q4 q3 q2 osc1 scs<1:0> program pc + 1 pc note 1: t t 1 p = 30.52 s. 2: t osc = 50 ns minimum. 3: t scs = 8 t t 1 p 4: t dly = 1 t t 1 p . q1 t1osi q1 t scs (3) counter q1 t t 1 p (1) system clock t osc (2) q3 q2 q4 q1 q2 pc + 2 pc + 3 q3 q4 q1 t dly (4)
? 2003 microchip technology inc. preliminary ds30498b-page 43 pic16f7x7 4.7.3 sec_run/rc_run to primary clock source when switching from a sec_run or rc_run mode back to the primary system clock, following a change of scs<1:0> to ? 00 ?, the sequence of events that take place will depend upon the value of the f osc bits in the configuration register. if the primary clock source is configured as a crystal (hs, xt or lp), then the transition will take place after 1024 clock cycles. this is necessary because the crystal oscillator has been pow- ered down until the time of the transition. in order to provide the system with a reliable clock when the changeover has occurred, the clock will not be released to the changeover circuit until the 1024 counts have expired. during the oscillator start-up time, the system clock comes from the current system clock. instruction exe- cution and/or peripheral operation continues using the currently selected oscillator as the cpu clock source until the necessary clock count has expired to ensure that the primary system clock is stable. to know when the ost has expired, the osts bit should be monitored. osts = 1 indicates that the oscillator start-up timer has timed out and the system clock comes from the primary clock source. following the oscillator start-up time, the internal q clocks are held in the q1 state until eight falling edge clocks are counted from the primary system clock. the clock input to the q clocks is then released and operation resumes with the primary system clock determined by the f osc bits (see figure 4-10). when in sec_run mode, the act of clearing the t1oscen bit in the t1con register will cause scs<0> to be cleared, which causes the scs<1:0> bits to revert to ? 00 ? or ? 10 ? depending on what scs<1> is. although the t1oscen bit was cleared, t1osc will be enabled and instruction execution will continue until the ost time-out for the main system clock is com- plete. at that time, the system clock will switch from the t1osc to the primary clock or the intrc. following this, the t1 oscillator will be shut down. 4.7.3.1 returning to primary clock source sequence changing back to the primary oscillator from sec_run or rc_run can be accomplished by either changing scs<1:0> to ? 00 ? or clearing the t1oscen bit in the t1con register (if t1osc was the secondary clock). the sequence of events that follows is the same for both modes: 1. if the primary system clock is configured as ec, rc or intrc, then the ost time-out is skipped. skip to step 3. 2. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active, waiting for 1024 clocks of the primary system clock. 3. on the following q1, the device holds the system clock in q1. 4. the device stays in q1 while eight falling edges of the primary system clock are counted. 5. once the eight counts transpire, the device begins to run from the primary oscillator. 6. if the secondary clock was intrc and the primary is not intrc, the intrc will be shut down to save current, providing that the intrc is not being used for any other function, such as wdt or fail-safe clock monitoring. 7. if the secondary clock was t1osc, the t1osc will continue to run if t1oscen is still set; otherwise, the t1 oscillator will be shut down. note: if the primary system clock is either rc or ec, an internal delay timer (5-10 s) will suspend operation after exiting secondary clock mode to allow the cpu to become ready for code execution.
pic16f7x7 ds30498b-page 44 preliminary ? 2003 microchip technology inc. figure 4-9: timing for transition between sec_run/rc_run and primary clock q4 q1 q3 q4 osc1 program pc pc + 1 sec. osc primary clock t ost (6) q1 pc + 3 t osc (3) t dly (5) t t 1 p (1) or t inp (2) t scs (4) q2 osc2 q3 q4 q1 osts system clock pc + 2 counter q2 q2 q3 q4 scs<1:0> note 1: t t 1 p = 30.52 s. 2: t inp = 32 s typical. 3: t osc = 50 ns minimum. 4: t scs = 8 t inp or 8t t 1 p . 5: t dly = 1 t inp or 1t t 1 p . 6: refer to parameter ?d032? in section 18.0 ?electrical characteristics? .
? 2003 microchip technology inc. preliminary ds30498b-page 45 pic16f7x7 4.7.3.2 returning to primary oscillator with a reset a reset will clear scs<1:0> back to ? 00 ?. the sequence for starting the primary oscillator following a reset is the same for all forms of reset, including por. there is no transition sequence from the alternate system clock to the primary system clock on a reset condition. instead, the device will reset the state of the osccon register and default to the primary system clock. the sequence of events that take place after this will depend upon the value of the f osc bits in the configuration register. if the external oscillator is configured as a crystal (hs, xt or lp), the cpu will be held in the q1 state until 1024 clock cycles have transpired on the primary clock. this is necessary because the crystal oscillator had been powered down until the time of the transition. during the oscillator start-up time, instruction execution and/or peripheral operation is suspended. if the primary system clock is either rc, ec or intrc, the cpu will begin operating on the first q1 cycle following the wake-up event. this means that there is no oscillator start-up time required because the pri- mary clock is already stable; however, there is a delay between the wake-up event and the following q2. an internal delay timer of 5-10 s will suspend operation after the reset to allow the cpu to become ready for code execution. the cpu and peripheral clock will be held in the first q1. the sequence of events is as follows: 1. a device reset is asserted from one of many sources (wdt, bor, mclr , etc.). 2. the device resets and the cpu start-up timer is enabled if in sleep mode. the device is held in reset until the cpu start-up time-out is complete. 3. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active waiting for 1024 clocks of the pri- mary system clock. while waiting for the ost, the device will be held in reset. the ost and cpu start-up timers run in parallel. 4. after both the cpu start-up and ost timers have timed out, the device will wait for one additional clock cycle and instruction execution will begin. figure 4-10: timing lp clock to primary system clock after reset (hs, xt, lp) note: if two-speed clock start-up mode is enabled, the intrc will act as the system clock until the ost timer has timed out. q4 q1 q3 q4 q1 q2 osc1 peripheral sleep program pc 0000h t1osi t ost (4) q3 t t 1 p (1) q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 clock counter 0004h 0005h 0003h q1 q2 q3 q4 reset t epu (3) note 1: t t 1 p = 30.52 s. 2: t osc = 50 ns minimum. 3: t epu = 5-10 s. 4: refer to parameter ?d032? in section 18.0 ?electrical characteristics? . cpu start-up t osc (2)
pic16f7x7 ds30498b-page 46 preliminary ? 2003 microchip technology inc. figure 4-11: timing lp clock to primary system clock after reset (ec, rc, intrc) q4 q1 q3 q4 q1 q2 osc1 program pc 0000h t1osi q3 t t 1 p (1) q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 counter 0003h 0004h 0002h q1 q2 q3 q4 mclr t cpu (2) note 1: t t 1 p = 30.52 s. 2: t cpu = 5-10 s. cpu start-up
? 2003 microchip technology inc. preliminary ds30498b-page 47 pic16f7x7 table 4-4: clock switching modes current system clock scs bits <1:0> modified to: delay osts bit iofs bit t1run bit new system clock comments lp, xt, hs, t1osc, ec, rc 10 (intrc) f osc <2:0> = lp, xt or hs 8 clocks of intrc 01 (1) 0 intrc or intosc or intosc postscaler the internal rc oscillator frequency is dependant upon the ircf bits. lp, xt, hs, intrc, ec, rc 01 (t1osc) f osc <2:0> = lp, xt or hs 8 clocks of t1osc 0 n/a 1 t1osc t1oscen bit must be enabled. intrc t1osc 00 f osc <2:0> = ec or f osc <2:0> = rc 8 clocks of ec or rc 1 n/a 0 ec or rc intrc t1osc 00 f osc <2:0> = lp, xt, hs 1024 clocks (ost) + 8 clocks of lp, xt, hs 1 n/a 0 lp, xt, hs during the 1024 clocks, program execution is clocked from the secondary oscillator until the primary oscillator becomes stable. lp, xt, hs 00 (due to reset) lp, xt, hs 1024 clocks (ost) 1 n/a 0 lp, xt, hs when a reset occurs, there is no clock transition sequence. instruction execution and/or peripheral operation is suspended unless two-speed start-up mode is enabled, after which the intrc will act as the system clock until the ost timer has expired. note 1: if the new clock source is intosc or intosc postscaler, then the iofs bit will be set 4 ms after the clock change.
pic16f7x7 ds30498b-page 48 preliminary ? 2003 microchip technology inc. 4.7.4 exiting sleep with an interrupt any interrupt, such as wdt or int0, will cause the part to leave the sleep mode. the scs bits are unaffected by a sleep command and are the same before and after entering and leaving sleep. the clock source used after an exit from sleep is determined by the scs bits. 4.7.4.1 sequence of events if scs<1:0> = 00 : 1. the device is held in sleep until the cpu start-up time-out is complete. 2. if the primary system clock is configured as an external oscillator (hs, xt, lp), then the ost will be active waiting for 1024 clocks of the primary system clock. while waiting for the ost, the device will be held in sleep unless two-speed start-up is enabled. the ost and cpu start-up timers run in parallel. refer to section 15.17.3 ?two-speed clock start-up mode? for details on two-speed start-up. 3. after both the cpu start-up and ost timers have timed out, the device will exit sleep and begin instruction execution with the primary clock defined by the f osc bits. if scs<1:0> = 01 or 10 : 1. the device is held in sleep until the cpu start-up time-out is complete. 2. after the cpu start-up timer has timed out, the device will exit sleep and begin instruction execution with the selected oscillator mode. note: if a user changes scs<1:0> just before entering sleep mode, the system clock used when exiting sleep mode could be different than the system clock used when entering sleep mode. as an example, if scs<1:0> = 01 , t1osc is the system clock and the following instructions are executed: bcf osccon,scs0 sleep then a clock change event is executed. if the primary oscillator is xt, lp or hs, the core will continue to run off t1osc and execute the sleep command. when sleep is exited, the part will resume operation with the primary oscillator after the ost has expired.
? 2003 microchip technology inc. preliminary ds30498b-page 49 pic16f7x7 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro ? mid-range mcu family reference manual, (ds33023). 5.1 porta and the trisa register porta is a 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the ra4 pin is multiplexed with the timer0 module clock input and one of the comparator outputs to become the ra4/t0cki/c1out pin. pins ra6 and ra7 are multiplexed with the main oscillator pins; they are enabled as oscillator or i/o pins by the selection of the main oscillator in configuration register 1h (see section 15.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as ? 0 ?. the other porta pins are multiplexed with analog inputs, the analog v ref + and v ref - inputs and the com- parator voltage reference output. the operation of pins ra3:ra0 and ra5 as a/d converter inputs is selected by clearing/setting the control bits in the adcon1 reg- ister (a/d control register 1). pins ra0 through ra5 may also be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. the ra4/t0cki/c1out pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the ra pins even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 5-1: initializing porta note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. bcf status, rp0 ; bcf status, rp1 ; bank0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x0f ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6>are always ; read as '0'.
pic16f7x7 ds30498b-page 50 preliminary ? 2003 microchip technology inc. figure 5-1: block diagram of ra0/an0:ra1/an1 pins figure 5-2: block diagram of ra3/an3/v ref + pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd i/o pin q d q ck input mode d q en to comparator ttl input buffer to a/d module channel input data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd i/o pin q d q ck input mode d q en to comparator ttl input buffer to a/d module channel input to a/d module v ref + input
? 2003 microchip technology inc. preliminary ds30498b-page 51 pic16f7x7 figure 5-3: block di agram of ra2/an2/v ref -/cv ref pin figure 5-4: block diagram of ra4/t0cki/c1out pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta analog v ss v dd ra2/an2/v ref -/ q d q ck d q en to comparator ttl input buffer input mode to a/d module channel input cvroe cv ref to a/d module v ref - cv ref pin data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta v ss ra4/t0cki/ q d q ck d q en tmr0 clock input comparator 1 output comparator mode = 011, 101, 001 1 0 analog input mode schmitt trigger input buffer c1out pin
pic16f7x7 ds30498b-page 52 preliminary ? 2003 microchip technology inc. figure 5-5: block diagra m of ra5/an4/lvdin/ss /c2out pin data bus q d q ck n wr porta wr trisa data latch tris latch rd trisa rd porta v ss ra5/an4/lvdin/ q d q ck d q en comparator 2 output comparator mode = 011, 101 1 0 analog input mode to a/d module channel input p v dd ss input lvdin ttl buffer ss /c2out pin
? 2003 microchip technology inc. preliminary ds30498b-page 53 pic16f7x7 figure 5-6: block diagram of osc2/clko/ra6 pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd osc2/clko q d q ck d q en ttl buffer oscillator circuit 1 0 era6 pin from osc1 (f osc = 1x1 ) emul (f osc = 1x0,011 ) p n v ss v dd emul + f osc = 00x, 010 (f osc = 1x0,011 ) 1 0 clko (f osc /4) (f osc = 1x1 ) v dd ra6 pin note 1: clko signal is 1/4 of the f osc frequency. (f osc = 1x1 ) emul + f osc = 00x,010 emul
pic16f7x7 ds30498b-page 54 preliminary ? 2003 microchip technology inc. figure 5-7: block diagram of osc1/clki/ra7 pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd osc1/clki q d q ck d q en oscillator circuit 1 0 era7 pin (f osc = 10x ) + emul nemul (f osc = 10x ) p n v ss v dd (f osc = 10x ) + emul (f osc = 10x ) v dd ra7 pin (f osc = 011 ) ttl buffer
? 2003 microchip technology inc. preliminary ds30498b-page 55 pic16f7x7 table 5-1: porta functions table 5-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/v ref -/cv ref bit 2 ttl input/output or analog input or v ref- . ra3/an3/v ref + bit 3 ttl input/output or analog input or v ref+. ra4/t0cki/c1out bit 4 st input/output or external clock input for timer0. output is open-drain type. ra5/an4/lvdin/ss /c2out bit 5 ttl input/output or slave select input for synchronous serial port or analog input. osc2/clko/ra6 bit 6 st input/output, connects to crystal or resonator, oscillator output or 1/4 the frequency of osc1 and denotes the instruction cycle in rc mode. osc1/clki/ra7 bit 7 st/cmos (1) input/output, connects to crystal or resonator or oscillator input. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 uu0u 0000 85h trisa porta data direction register 1111 1111 1111 1111 9fh adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d converter must be set to one of the following modes, where pcfg2:pcfg0 = 100, 101, 11x .
pic16f7x7 ds30498b-page 56 preliminary ? 2003 microchip technology inc. 5.2 portb and the trisb register portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. portb pins are multiplexed with analog inputs. the operation of each pin is selected by clearing/setting the appropriate control bits in the adcon1 register. four of the portb pins (rb7:rb4) have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. this interrupt on mismatch feature, together with soft- ware configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the application note an552, ? implementing wake-up on key stroke ? (ds00552). rb0/int is an external interrupt input pin and is configured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 15.15.1 ?int interrupt? . portb is multiplexed with several peripheral functions (see table 5-3). portb pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portb pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisb as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. note: on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 57 pic16f7x7 figure 5-8: block diag ram of rb0/int/an12 pin figure 5-9: block diag ram of rb1/an10 pin note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. data latch rbpu (1) p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb i/o pin tris latch to i n t ttl input buffer input mode analog input mode analog to a/d channel input input mode analog note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. data latch rbpu (1) p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb i/o pin tris latch ttl input buffer input mode analog to a/d channel input input mode analog
pic16f7x7 ds30498b-page 58 preliminary ? 2003 microchip technology inc. figure 5-10: block diag ram of rb2/an8 pin note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. data latch p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb i/o pin tris latch ttl input buffer input mode analog to a/d channel input rbpu (1)
? 2003 microchip technology inc. preliminary ds30498b-page 59 pic16f7x7 figure 5-11: block diagram of rb3/ccp2/an9 pin data latch p v dd q d ck q d ck q d en data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb to a/d channel input i/o pin schmitt trigger buffer tris latch note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. 2: the sda schmitt conforms to the i 2 c specification. 1 0 ccp2 output p n v ss v dd q ccp2 output select and ccpmx ttl input buffer input mode analog input mode analog input mode analog to ccp module input rbpu (1)
pic16f7x7 ds30498b-page 60 preliminary ? 2003 microchip technology inc. figure 5-12: block diag ram of rb4/an11 pin data latch from other p v dd i/o pin q d ck q d ck qd en qd en data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. 2: the scl schmitt conforms to the i 2 c specification. to a/d channel input p n v ss v dd input mode analog ttl input buffer input mode analog input mode analog rbpu (1)
? 2003 microchip technology inc. preliminary ds30498b-page 61 pic16f7x7 figure 5-13: block diagra m of rb5/an13/ccp3 pin data latch from other rbpu (1) p v dd i/o pin q d ck q d ck qd en qd en data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. ccp3 output 1 0 ccp3 output select ttl input buffer input mode analog input mode analog schmitt trigger buffer input mode analog to ccp module input input mode analog to a/d channel input
pic16f7x7 ds30498b-page 62 preliminary ? 2003 microchip technology inc. figure 5-14: block diagram of rb6/pgc pin data latch from other rbpu (1) p v dd i/o pin q d ck q d ck qd en qd en data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. ttl input buffer schmitt trigger buffer pgc program mode/icd program mode/icd
? 2003 microchip technology inc. preliminary ds30498b-page 63 pic16f7x7 figure 5-15: block diagram of rb7/pgd pin data latch from other rbpu (1) p v dd i/o pin q d ck q d ck qd en qd en data bus wr portb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch q3 q1 note 1: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit. pgd pgd 1 0 port /program mode/icd ttl input buffer 1 0 pgd drven program mode/icd wr trisb
pic16f7x7 ds30498b-page 64 preliminary ? 2003 microchip technology inc. table 5-3: portb functions table 5-4: summary of registers associated with portb name bit# buffer function rb0/int/an12 bit 0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up or analog input. rb1/an10 bit 1 ttl input/output pin. internal software programmable weak pull-up or analog input. rb2/an8 bit 2 ttl input/output pin. internal software programmable weak pull-up or analog input. rb3/ccp2/an9 bit 3 ttl input/output pin or capture 2 input/compare 2 output/pwm 2 output. internal software programmable weak pull-up or analog input. rb4/an11 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up or analog input. rb5/an13/ccp3 bit 5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up or analog input or capture 2 input/ compare 2 output/pwm 2 output. rb6/pgc bit 6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7/pgd bit 7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xx00 0000 uu00 0000 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 9fh adcon1 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 2003 microchip technology inc. preliminary ds30498b-page 65 pic16f7x7 5.3 portc and the trisc register portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 5-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings and to section 16.1 ?read-modify- write operations? for additional information on read-modify-write operations. figure 5-16: portc block diagram (peripheral output override) rc<2:0>, rc<7:5> pins figure 5-17: portc block diagram (peripheral output override) rc<4:3> pins port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. tris port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd vss port peripheral oe (3) sspl input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. 0 1 cke sspstat<6> schmitt trigger with smbus levels tris
pic16f7x7 ds30498b-page 66 preliminary ? 2003 microchip technology inc. table 5-5: portc functions table 5-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit 1 st input/output port pin or timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 bit 2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit 6 st input/output port pin or usar t asynchronous transmit or synchronous clock. rc7/rx/dt bit 7 st input/output port pin or usart asynchronous receive or synchronous data. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
? 2003 microchip technology inc. preliminary ds30498b-page 67 pic16f7x7 5.4 portd and trisd registers this section is not applicable to the pic16f737 or pic16f767. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configureable as an input or output. portd can be configured as an 8-bit wide micro- processor port (parallel slave port) by setting control bit, pspmode (trise<4>). in this mode, the input buffers are ttl. figure 5-18: portd block diagram (in i/o port mode) table 5-7: portd functions table 5-8: summary of registers associated with portd data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en name bit# buffer type function rd0/psp0 bit 0 st/ttl (1) input/output port pin or parallel slave port bit 0. rd1/psp1 bit 1 st/ttl (1) input/output port pin or parallel slave port bit 1. rd2/psp2 bit 2 st/ttl (1) input/output port pin or parallel slave port bit 2. rd3/psp3 bit 3 st/ttl (1) input/output port pin or parallel slave port bit 3. rd4/psp4 bit 4 st/ttl (1) input/output port pin or parallel slave port bit 4. rd5/psp5 bit 5 st/ttl (1) input/output port pin or parallel slave port bit 5. rd6/psp6 bit 6 st/ttl (1) input/output port pin or parallel slave port bit 6. rd7/psp7 bit 7 st/ttl (1) input/output port pin or parallel slave port bit 7. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode ? (1) porte data direction bits 0000 1111 0000 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by portd. note 1: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
pic16f7x7 ds30498b-page 68 preliminary ? 2003 microchip technology inc. 5.5 porte and trise register this section is not applicable to the pic16f737 or pic16f767. porte has four pins, re0/rd /an5, re1/wr /an6, re2/cs /an7 and mclr /v pp /re3, which are individu- ally configureable as inputs or outputs. these pins have schmitt trigger input buffers. re3 is only available as an input if mclre is ? 0 ? in configuration word 1. i/o porte becomes control inputs for the micro- processor port when bit, pspmode (trise<4>), is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs). ensure adcon1 is configured for digital i/o. in this mode, the input buffers are ttl. register 5-1 shows the trise register, which also controls the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected as an analog input, these pins will read as ? 0 ?s. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 5-19: port e block diagram (in i/o port mode) table 5-9: porte functions table 5-10: summary of registers associated with porte note: on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en name bit# buffer type function re0/rd /an5 bit 0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input. for rd (psp mode): 1 = idle 0 = read operation. contents of portd register output to portd i/o pins (if chip selected). re1/wr /an6 bit 1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input. for wr (psp mode): 1 =idle 0 = write operation. value of portd i/o pins latched into portd register (if chip selected). re2/cs /an7 bit 2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input. for cs (psp mode): 1 = device is not selected 0 = device is selected mclr /v pp /re3 bit 3 st input, master clear (reset) or programming input voltage. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte ? ? ? ? re3 re2 re1 re0 ---- x000 ---- -uuu 89h trise ibf obf ibov pspmode ? (1) porte data direction bits 0000 1111 0000 1111 9fh adcon1 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by porte. note 1: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 69 pic16f7x7 register 5-1: trise register (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? (1) trise2 trise1 trise0 bit 7 bit 0 bit 7 parallel slave port status/control bits: ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented : read as ? 1 ? (1) note 1: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?. bit 2 porte data direction bits: trise2: direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1 trise1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0 trise0 : direction control bit for pin re0/rd /an5 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 70 preliminary ? 2003 microchip technology inc. 5.6 parallel slave port the parallel slave port (psp) is not implemented on the pic16f737 or pic16f767. portd operates as an 8-bit wide parallel slave port or microprocessor port when control bit, pspmode (trise<4>), is set. in slave mode, it is asynchronously readable and writable by an external system using the read control input pin re0/rd /an5, the write control input pin re1/wr /an6 and the chip select control input pin re2/cs /an7. the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd /an5 to be the rd input, re1/wr /an6 to be the wr input and re2/cs /an7 to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (i.e., set). the a/d port configuration bits, pcfg3:pcfg0 (adcon1<3:0>), must be set to configure pins re2:re0 as digital i/o. there are actually two 8-bit latches, one for data output (external reads) and one for data input (external writes). the firmware writes 8-bit data to the portd output data latch and reads data from the portd input data latch (note that they have the same address). in this mode, the trisd register is ignored since the external device is controlling the direction of data flow. an external write to the psp occurs when the cs and wr lines are both detected low. firmware can read the actual data on the portd pins during this time. when either the cs or wr lines become high (level trig- gered), the data on the portd pins is latched and the input buffer full (ibf) status flag bit (trise<7>) and interrupt flag bit, pspif (pir1<7>), are set on the q4 clock cycle following the next q2 cycle to signal the write is complete (figure 5-21). firmware clears the ibf flag by reading the latched portd data and clears the pspif bit. the input buffer overflow (ibov) status flag bit (trise<5>) is set if an external write to the psp occurs while the ibf flag is set from a previous external write. the previous portd data is overwritten with the new data. ibov is cleared by reading portd and clearing ibov. a read from the psp occurs when both the cs and rd lines are detected low. the data in the portd output latch is output to the portd pins. the output buffer full (obf) status flag bit (trise<6>) is cleared imme- diately (figure 5-22), indicating that the portd latch is being read or has been read by the external bus. if firmware writes new data to the output latch during this time, it is immediately output to the portd pins but obf will remain cleared. when either the cs or rd pins are detected high, the portd outputs are disabled and the interrupt flag bit pspif is set on the q4 clock cycle following the next q2 cycle, indicating that the read is complete. obf remains low until firmware writes new data to portd. when not in psp mode, the ibf and obf bits are held clear. flag bit ibov remains unchanged. the pspif bit must be cleared by the user in firmware; the interrupt can be disabled by clearing the interrupt enable bit, pspie (pie1<7>). figure 5-20: portd and porte block diagram (parallel slave port) data bus wr port rd rdx pin q d ck en qd en port one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl
? 2003 microchip technology inc. preliminary ds30498b-page 71 pic16f7x7 figure 5-21: parallel slave port write waveforms figure 5-22: parallel slave port read waveforms table 5-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? re3 re2 re1 re0 ---- x000 ---- x000 89h trise ibf obf ibov pspmode ? (2) porte data direction bits 0000 1111 0000 1111 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. note 1: bits pspie and pspif are reserved on the pic16f737/767; always maintain these bits clear. 2: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
pic16f7x7 ds30498b-page 72 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 73 pic16f7x7 6.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock additional information on the timer0 module is available in the picmicro ? mid-range mcu family reference manual (ds33023). figure 6-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. 6.1 timer0 operation timer0 operation is controlled through the option_reg register (see register 2-2). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit, t0cs (option_reg<5>). in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki/c1out. the incrementing edge is deter- mined by the timer0 source edge select bit, t0se (option_reg<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.3 ?using timer0 with an external clock? . the prescaler is mutually, exclusively shared between the timer0 module and the watchdog timer. the prescaler is not readable or writable. section 6.4 ?prescaler? details the operation of the prescaler. 6.2 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit tmr0if (intcon<2>). the interrupt can be masked by clearing bit tmr0ie (intcon<5>). bit tmr0if must be cleared in software by the timer0 module interrupt service routine before re-enabling this inter- rupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut-off during sleep. figure 6-1: block diagram of the timer0/wdt prescaler ra4/t0cki/c1out t0se pin m u x clko (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1 mux m u x mux psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa and ps2:ps0 are (option_reg<5:0>). psa m u x 0 1 0 1 data bus set flag bit tmr0if on overflow 8 psa t0cs prescaler 31.25 khz wdt timer wdt enable bit 16-bit prescaler
pic16f7x7 ds30498b-page 74 preliminary ? 2003 microchip technology inc. 6.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 20 ns) and low for at least 2 t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 6.4 prescaler there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that the prescaler cannot be used by the watchdog timer and vice versa. this prescaler is not readable or writable (see figure 6-1). the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. note: although the prescaler can be assigned to either the wdt or timer0, but not both, a new divide counter is implemented in the wdt circuit to give multiple wdt time-out selections. this allows tmr0 and wdt to each have their own scaler. refer to section 15.17 ?watchdog timer (wdt)? for further details. note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment.
? 2003 microchip technology inc. preliminary ds30498b-page 75 pic16f7x7 register 6-1: option_reg register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa (1) ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit (1) 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module note 1: to avoid an unintended device reset, the instruction sequence shown in the picmicro ? mid-range mcu family reference manual (ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. bit 2-0 ps<2:0>: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16f7x7 ds30498b-page 76 preliminary ? 2003 microchip technology inc. example 6-1: changing the prescaler assignment from wdt to timer0 table 6-1: registers associated with timer0 clrwdt ; clear wdt and prescaler banksel option ; select bank of option movlw b'xxxx0xxx' ; select tmr0, new prescale movwf option ; value and clock source address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h,101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0.
? 2003 microchip technology inc. preliminary ds30498b-page 77 pic16f7x7 7.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit, tmr1ie (pie1<0>). the timer1 oscillator can be used as a secondary clock source in low-power modes. when the t1run bit is set along with scs<1:0> = 01 , the timer1 oscillator is pro- viding the system clock. if the fail-safe clock monitor is enabled and the timer1 oscillator fails while providing the system clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. 7.1 timer1 operation timer1 can operate in one of three modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit, tmr1on (t1con<0>). timer1 also has an internal ?reset input?. this reset can be generated by the ccp1 module as the special event trigger (see section 9.4 ?capture mode? ). register 7-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc0/t1oso/t1cki and rc1/t1osi/ccp2 pins become inputs. that is, the trisb<7:6> value is ignored and these pins read as ? 0 ?. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023).
pic16f7x7 ds30498b-page 78 preliminary ? 2003 microchip technology inc. register 7-1: t1con: timer1 control regist er (address 10h) u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 t1run : timer1 system clock status bit 1 = system clock is derived from timer1 oscillator 0 = system clock is derived from another source bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 =stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 79 pic16f7x7 7.2 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit, t1sync (t1con<2>), has no effect since the internal clock is always in sync. 7.3 timer1 counter operation timer1 may operate in asynchronous or synchronous mode depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. 7.4 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration during sleep mode, timer1 will not increment, even if the external clock is present since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 7-1: timer1 incrementing edge figure 7-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1osi t1oso/t1cki note 1: when the t1oscen bit is cleared, the inverter is turned off. this e liminates power drain. set flag bit tmr1if on overflow tmr1
pic16f7x7 ds30498b-page 80 preliminary ? 2003 microchip technology inc. 7.5 timer1 operation in asynchronous counter mode if control bit, t1sync (t1con<2>), is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow that will wake-up the processor. however, special precautions in software are needed to read/write the timer ( section 7.5.1 ?reading and writing timer1 in asynchronous counter mode? ). in asynchronous counter mode, timer1 cannot be used as a time base for capture or compare operations. 7.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. the example codes provided in example 7-1 and example 7-2 demonstrate how to write to and read timer1 while it is running in asynchronous mode. example 7-1: writing a 16-bit free running timer example 7-2: reading a 16-bit free running timer ; all interrupts are disabled clrf tmr1l ; clear low byte, ensures no rollover into tmr1h movlw hi_byte ; value to load into tmr1h movwf tmr1h, f ; write high byte movlw lo_byte ; value to load into tmr1l movwf tmr1h, f ; write low byte ; re-enable the interrupt (if required) continue ; continue with your code ; all interrupts are disabled movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl movf tmr1h, w ; read high byte subwf tmph, w ; sub 1st read with 2nd read btfsc status,z ; is result = 0 goto continue ; good 16-bit read ; tmr1l may have rolled over between the read of the high and low bytes. ; reading the high and low bytes now will read a good value. movf tmr1h, w ; read high byte movwf tmph movf tmr1l, w ; read low byte movwf tmpl ; re-enable the interrupt (if required) continue ; continue with your code
? 2003 microchip technology inc. preliminary ds30498b-page 81 pic16f7x7 7.6 timer1 oscillator a crystal oscillator circuit is built between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit, t1oscen (t1con<3>). the oscil- lator is a low-power oscillator, rated up to 32.768 khz. it will continue to run during all power managed modes. it is primarily intended for a 32 khz crystal. the circuit for a typical lp oscillator is shown in figure 7-3. table 7-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper oscillator start-up. figure 7-3: external components for the timer1 lp oscillator table 7-1: capacitor selection for the timer1 oscillator 7.7 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power dur- ing operation. due to the low-power nature of the oscil- lator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 7-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor, a grounded guard ring around the oscillator circuit, as shown in figure 7-4, may be helpful when used on a single sided pcb or in addition to a ground plane. figure 7-4: oscillator circuit with grounded guard ring 7.8 resetting timer1 using a ccp trigger output if the ccp1 module is configured in compare mode to generate a ?special event trigger" signal (ccp1m3:ccp1m0 = 1011 ), the signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. osc type freq c1 c2 lp 32 khz 33 pf 33 pf note 1: microchip suggests this value as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. pic16f7x7 t1osi t1oso c2 33 pf c1 33 pf xtal 32.768 khz note: see the notes with table 7-1 for additiona l information about capacitor selection. note: the special event triggers from the ccp1 module will not set interrupt flag bit, tmr1if (pir1<0>). osc1 v ss osc2 rc0 rc1 rc2
pic16f7x7 ds30498b-page 82 preliminary ? 2003 microchip technology inc. 7.9 resetting timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 7.10 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. 7.11 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 7.6 ?timer1 oscillator? ) gives users the option to include rtc functionality in their applications. this is accomplished with an inex- pensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 7-3, demonstrates a simple method to incre- ment a counter at one-second intervals using an inter- rupt service routine. incrementing the tmr1 register pair to overflow, triggers the interrupt and calls the rou- tine which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflows. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the msbit of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ) as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. example 7-3: implementing a real-time clock using a timer1 interrupt service rtcinit banksel tmr1h movlw 0x80 ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins movlw .12 movwf hours banksel pie1 bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr banksel tmr1h bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movf secs, w sublw .60 btfss status, z ; 60 seconds elapsed? return ; no, done clrf seconds ; clear seconds incf mins, f ; increment minutes movf mins, w sublw .60 btfss status, z ; 60 seconds elapsed? return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movf hours, w sublw .24 btfss status, z ; 24 hours elapsed? return ; no, done clrf hours ; clear hours return ; done
? 2003 microchip technology inc. preliminary ds30498b-page 83 pic16f7x7 table 7-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on -000 0000 -uuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the pic16f737/767 devices; always maintain these bits clear.
pic16f7x7 ds30498b-page 84 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 85 pic16f7x7 8.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time base for the pwm mode of the ccp module(s). the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt, latched in flag bit, tmr2if (pir1<1>). timer2 can be shut-off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. register 8-1 shows the timer2 control register. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). 8.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. 8.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssp module which optionally uses it to generate the shift clock. figure 8-1: timer2 block diagram comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. 1:1 to 1:16 t2outps3: t2outps0 t2ckps1: t2ckps0
pic16f7x7 ds30498b-page 86 preliminary ? 2003 microchip technology inc. register 8-1: t2con: timer2 control regist er (address 12h) table 8-1: registers associated with timer2 as a timer/counter u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16f737/767 devices; always maintain these bits clear.
? 2003 microchip technology inc. preliminary ds30498b-page 87 pic16f7x7 9.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register the ccp1, ccp2 and ccp3 modules are identical in operation, with the exception being the operation of the special event trigger. table 9-1 and table 9-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 and ccp3 operate the same as ccp1, except where noted. 9.1 ccp1 module capture/compare/pwm register 1 (ccpr1) is comprised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register con- trols the operation of ccp1. the special event trigger is generated by a compare match and will clear both tmr1h and tmr1l registers. 9.2 ccp2 module capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is gen- erated by a compare match; it will clear both tmr1h and tmr1l registers and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the picmicro ? mid-range mcu family reference manual (ds33023) and in application note an594, ?using the ccp module(s)? (ds00594). 9.3 ccp3 module capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp3con register controls the operation of ccp3. table 9-1: ccp mode ? timer resources required table 9-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time base. capture compare same tmr1 time base. compare compare same tmr1 time base. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). the rising edges are aligned. pwm capture none. pwm compare none.
pic16f7x7 ds30498b-page 88 preliminary ? 2003 microchip technology inc. register 9-1: ccpxcon register (address 17h, 1dh, 97h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ccpxx:ccpxy : pwm least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 clears timer1; ccp2 clears timer1 and starts an a/d conversion (if a/d module is enabled) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 89 pic16f7x7 9.4 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as one of the following and is configured by ccpxcon<3:0>: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits, ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit, ccp1if (pir1<2>), is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 9.4.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be configured as an input by setting the trisc<2> bit. figure 9-1: capture mode operation block diagram 9.4.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 9.4.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit, ccp1ie (pie1<2>), clear to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. 9.4.4 ccp prescaler there are four prescaler settings specified by bits, ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 9-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 9-1: changing between capture prescalers 9.5 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits, ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 9-2: compare mode operation block diagram note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q?s ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccp1con ;load ccp1con with this ;value ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: clear tmr1h and tmr1l registers not set interrupt flag bit, tmr1f (pir1<0>) (for ccp2 only) set the go/done bit (adcon0<2>)
pic16f7x7 ds30498b-page 90 preliminary ? 2003 microchip technology inc. 9.5.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an output by clearing the trisc<2> bit. 9.5.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 9.5.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccp1if or ccp2if bit is set, causing a ccp interrupt (if enabled). 9.5.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). table 9-3: registers associated with capture, compare and timer1 note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. note: the special event trigger from the ccp1 and ccp2 modules will not set interrupt flag bit, tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 osfif cmif lvdif ?bclif ? ccp3if ccp2if 000- 0--0 000- 0--0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 osfie cmie lvdie ?bclie ?ccp3ieccp2ie 000- 0--0 000- 0--0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 95h ccpr3l capture/compare/pwm register 3 (lsb) xxxx xxxx uuuu uuuu 96h ccpr3h capture/compare/pwm register 3 (msb) xxxx xxxx uuuu uuuu 97h ccp3con ? ? ccp3x ccp3y ccp3m3 ccp3m2 ccp3m1 ccp3m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by capture and timer1. note 1: the psp is not implemented on the pic16f737/767 devices; always maintain these bits clear.
? 2003 microchip technology inc. preliminary ds30498b-page 91 pic16f7x7 9.6 pwm mode (pwm) in pulse width modulation mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 9-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 9.6.3 ?setup for pwm operation? . figure 9-3: simplified pwm block diagram a pwm output (figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 9-4: pwm output 9.6.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 9.6.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the formula: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 (note 1) note 1: the 8-bit timer is concatenated with the 2-bit internal q clock or the 2 bits of the prescaler to create the 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 tmr2 reset tmr2 reset note: the timer2 postscaler (see section 9.4 ?capture mode? ) is not used in the deter- mination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits = resolution
pic16f7x7 ds30498b-page 92 preliminary ? 2003 microchip technology inc. 9.6.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 9-4: example pwm frequencies and resolutions (f osc = 20 mhz) table 9-5: registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 osfif cmif lvdif ? bclif ? ccp3if ccp2if 000- 0-00 000- 0-00 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 osfie cmie lvdie ? bclie ? ccp3ie ccp2ie 000- 0-00 000- 0-00 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module register 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 95h ccpr3l capture/compare/pwm register 3 (lsb) xxxx xxxx uuuu uuuu 96h ccpr3h capture/compare/pwm register 3 (msb) xxxx xxxx uuuu uuuu 97h ccp3con ? ? ccp3x ccp3y ccp3m3 ccp3m2 ccp3m1 ccp3m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16f737/767 devices; always maintain these bits clear.
? 2003 microchip technology inc. preliminary ds30498b-page 93 pic16f7x7 10.0 master synchronous serial port (mssp) module 10.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi?) inter-integrated circuit (i 2 c?) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 10.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon and sspcon2). the use of these registers and their individual configuration bits differ significantly, depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 10.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) ? rc5/sdo serial data in (sdi) ? rc4/sdi/sda serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ? ra5/an4/lvdin/ss /c2out figure 10-1 shows the block diagram of the mssp module when operating in spi mode. figure 10-1: mssp block diagram (spi mode) note: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the state of the ss pin can affect the state read back from the trisc<5> bit. the peripheral oe signal, from the ssp mod- ule into portc, controls the state that is read back from the trisc<5> bit (see section 5.3 ?portc and the trisc register? for information on portc). if read-modify-write instructions, such as bsf are performed on the trisc register while the ss pin is high, this will cause the trisc<5> bit to be set, thus disabling the sdo output. read write internal data bus sspsr reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke rc4/sdi/ rc5/sdo ra5/an4/ ( ) sspbuf reg lvdin/ss/ rc3/ sck/ peripheral oe c2out sda scl
pic16f7x7 ds30498b-page 94 preliminary ? 2003 microchip technology inc. 10.3.1 registers the mssp module has four registers for spi mode operation. these are: mssp control register (sspcon) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) ? not directly accessible sspcon and sspstat are the control and status registers in spi mode operation. the sspcon register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 10-1: sspstat: mssp status (spi mode) register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock edge select bit when ckp = 0 : 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck when ckp = 1 : 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write bit information used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 95 pic16f7x7 register 10-2: sspcon: mssp control (spi mode) register 1 (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word. (must be cleared in software.) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. (must be cleared in software.) 0 = no overflow note: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 96 preliminary ? 2003 microchip technology inc. 10.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon<5:0> and sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 10-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 10-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2003 microchip technology inc. preliminary ds30498b-page 97 pic16f7x7 10.3.3 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisa<5> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 10.3.4 typical connection figure 10-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? slave sends dummy data master sends data ? slave sends data master sends dummy data ? slave sends data figure 10-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010xb serial clock
pic16f7x7 ds30498b-page 98 preliminary ? 2003 microchip technology inc. 10.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 10-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon<4>). this then, would give waveforms for spi communication as shown in figure 10-3, figure 10-5 and figure 10-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 10-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 10-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2
? 2003 microchip technology inc. preliminary ds30498b-page 99 pic16f7x7 10.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times, as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 10.3.7 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon<3:0> = 4h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 10-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2
pic16f7x7 ds30498b-page 100 preliminary ? 2003 microchip technology inc. figure 10-5: spi mode waveform (slave mode with cke = 0 ) figure 10-6: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
? 2003 microchip technology inc. preliminary ds30498b-page 101 pic16f7x7 10.3.8 sleep operation in master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device from sleep. 10.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 10.3.10 bus mode compatibility table 10-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 10-1: spi bus modes there is also an smp bit which controls when the data is sampled. table 10-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa porta data direction register 1111 1111 1111 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi mode. note 1: the pspif, pspie and pspip bits are reserved on 28-pin devices; always maintain these bits clear.
pic16f7x7 ds30498b-page 102 preliminary ? 2003 microchip technology inc. 10.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) ? rc3/sck/scl serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs or outputs through the trisc<4:3> bits. figure 10-7: mssp block diagram (i 2 c mode) 10.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register (sspcon) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) ? not directly accessible mssp address register (sspadd) sspcon, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the ssp is configured in i 2 c slave mode. when the ssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/ rc4/ shift clock msb sdi/ lsb sda scl
? 2003 microchip technology inc. preliminary ds30498b-page 103 pic16f7x7 register 10-3: sspstat: mssp status (i 2 c mode) register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 2 r/w : read/write bit information bit (i 2 c mode only) in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty in receive mode: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 104 preliminary ? 2003 microchip technology inc. register 10-4: sspcon: mssp control (i 2 c mode) register 1 (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started. (must be cleared in software.) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word. (must be cleared in software.) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. (must be cleared in software.) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, the sda and scl pins must be properly configured as input or output. bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note: bit combinations not specifically listed here are either reserved or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 105 pic16f7x7 register 10-5: sspcon2: mssp control (i 2 c mode) register 2 (address 91h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled/stretch enabled bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is enabled for slave transmit only (pic16f87x compatibility) note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 106 preliminary ? 2003 microchip technology inc. 10.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon<5>). the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = osc/4 (sspadd + 1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open-drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 10.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspstat<0>), was set before the transfer was received. the overflow bit, sspov (sspcon<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. 10.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incom- ing bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is com- pared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif.
? 2003 microchip technology inc. preliminary ds30498b-page 107 pic16f7x7 10.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit, sspif (pir1<3>), must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspcon<4>). see section 10.4.4 ?clock stretching? for more detail. 10.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regard- less of sen (see section 10.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp (sspcon<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 10-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is com- plete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse.
pic16f7x7 ds30498b-page 108 preliminary ? 2003 microchip technology inc. figure 10-8: i 2 c slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon<6>) s 1 2 34 56 7 8 91 234 5 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 )
? 2003 microchip technology inc. preliminary ds30498b-page 109 pic16f7x7 figure 10-9: i 2 c slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software while cpu responds to sspif scl held low
pic16f7x7 ds30498b-page 110 preliminary ? 2003 microchip technology inc. figure 10-10: i 2 c slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place
? 2003 microchip technology inc. preliminary ds30498b-page 111 pic16f7x7 figure 10-11: i 2 c slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon<4>) ckp is set in software ckp is automatically cleared in hardware holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bf flag is clear third address sequence at the end of the
pic16f7x7 ds30498b-page 112 preliminary ? 2003 microchip technology inc. 10.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 10.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock, at the end of the ack sequence if the bf bit is set, the ckp bit in the sspcon register is automati- cally cleared, forcing the scl output to be held low. the ckp being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before recep- tion is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 10-13). 10.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address, with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 10.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock, if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 10-9). 10.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is con- trolled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence, which contains the high order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 10-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
? 2003 microchip technology inc. preliminary ds30498b-page 113 pic16f7x7 10.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to ? 0 ?; however, setting the ckp bit will not assert the scl output low until the scl output is already sam- pled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 10-12). figure 10-12: clock synchronization timing sda scl dx-1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock
pic16f7x7 ds30498b-page 114 preliminary ? 2003 microchip technology inc. figure 10-13: i 2 c slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon<6>) s 1 234 56 7 8 9 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs
? 2003 microchip technology inc. preliminary ds30498b-page 115 pic16f7x7 figure 10-14: i 2 c slave mode timing with sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 789 12345 67 89 1 2345 78 9 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
pic16f7x7 ds30498b-page 116 preliminary ? 2003 microchip technology inc. 10.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set and while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 10-15). figure 10-15: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt ? 0 ? ? 1 ?
? 2003 microchip technology inc. preliminary ds30498b-page 117 pic16f7x7 10.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options: 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register, initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 10-16: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condi- tion is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, start bit detect sspbuf internal data bus set/reset s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0
pic16f7x7 ds30498b-page 118 preliminary ? 2003 microchip technology inc. 10.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate a receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode opera- tion is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 10.4.7 ?baud rate generator? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete.
? 2003 microchip technology inc. preliminary ds30498b-page 119 pic16f7x7 10.4.7 baud rate generator in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 10-17). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 10-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. figure 10-17: baud rate generator block diagram table 10-3: i 2 c clock rate w/brg f cy f cy * 2 brg value f scl (2 rollovers of brg) 10 mhz 20 mhz 19h 400 khz (1) 10 mhz 20 mhz 20h 312.5 khz 10 mhz 20 mhz 3fh 100 khz 4 mhz 8 mhz 0ah 400 khz (1) 4 mhz 8 mhz 0dh 308 khz 4 mhz 8 mhz 28h 100 khz 1 mhz 2 mhz 03h 333 khz (1) 1 mhz 2 mhz 0ah 100 khz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload
pic16f7x7 ds30498b-page 120 preliminary ? 2003 microchip technology inc. 10.4.7.1 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 10-18). figure 10-18: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 2003 microchip technology inc. preliminary ds30498b-page 121 pic16f7x7 10.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start con- dition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the con- tents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hard- ware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 10.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 10-19: first start bit timing note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
pic16f7x7 ds30498b-page 122 preliminary ? 2003 microchip technology inc. 10.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 10.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 10-20: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low-to-high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock. end of xmit. at completion of start bit, hardware clears rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1 , sda = 1 , scl (no change). scl = 1 occurs here. t brg t brg t brg and sets sspif
? 2003 microchip technology inc. preliminary ds30498b-page 123 pic16f7x7 10.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter #106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter #107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurred or if data was received prop- erly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 10-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 10.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 10.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 10.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. 10.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/ low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate gener- ator is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 10.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 10.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 10.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic16f7x7 ds30498b-page 124 preliminary ? 2003 microchip technology inc. figure 10-21: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half of 10-bit address r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w starts transmit scl held low while cpu responds to sspif sen = 0 write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 2003 microchip technology inc. preliminary ds30498b-page 125 pic16f7x7 figure 10-22: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ). write to sspbuf occurs here. ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit. sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition. cleared in software sda = ackdt = 0
pic16f7x7 ds30498b-page 126 preliminary ? 2003 microchip technology inc. 10.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 10-23). 10.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 10.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sam- pled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 10-24). 10.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 10-23: acknowledge sequence waveform figure 10-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1 , ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software scl sda sda asserted low before rising edge of clock to setup stop condition write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 2003 microchip technology inc. preliminary ds30498b-page 127 pic16f7x7 10.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 10.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 10.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration to see if the signal level is at the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 10.4.17 multi-master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state (figure 10-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determi- nation of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register or the bus is idle and the s and p bits are cleared. figure 10-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven set bus collision interrupt (bclif) by the master. bus collision has occurred. by master data changes while scl = 0
pic16f7x7 ds30498b-page 128 preliminary ? 2003 microchip technology inc. 10.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 10-26). b) scl is sampled low before sda is asserted low (figure 10-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted, the bclif flag is set and the mssp module is reset to its idle state (figure 10-26). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 10-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0 and during this time, if the scl pin is sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 10-26: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address fol- lowing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module resets into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif.
? 2003 microchip technology inc. preliminary ds30498b-page 129 pic16f7x7 figure 10-27: bus collision d uring start condition (scl = 0 ) figure 10-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , sda pulled low by other master. reset brg and assert sda. scl pulled low after brg time-out set sspif ? 0 ? set sen, enable start sequence if sda = 1 , scl = 1
pic16f7x7 ds30498b-page 130 preliminary ? 2003 microchip technology inc. 10.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, see figure 10-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high- to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (figure 10-30). if at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 10-29: bus collision during a repeat ed start condition (case 1) figure 10-30: bus collision during a repe ated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? s sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
? 2003 microchip technology inc. preliminary ds30498b-page 131 pic16f7x7 10.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 10-31). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 10-32). figure 10-31: bus collision during a stop condition (case 1) figure 10-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
pic16f7x7 ds30498b-page 132 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 133 pic16f7x7 11.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full-duplex) synchronous ? master (half-duplex) synchronous ? slave (half-duplex) bit spen (rcsta<7>) and bits trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchronous receiver transmitter. the usart module also has a multi-processor communication capability using 9-bit address detection. register 11-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data, can be parity bit legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 134 preliminary ? 2003 microchip technology inc. register 11-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, enables interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receiving next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data (can be parity bit, but must be calculated by user firmware) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 135 pic16f7x7 11.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free-running 8-bit timer. in asynchro- nous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 11-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 11-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1 ), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 11.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 11-1: baud rate formula table 11-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x + 1)) (synchronous) baud rate = f osc /(4(x + 1)) baud rate = f osc /(16(x + 1)) n/a x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used by the brg.
pic16f7x7 ds30498b-page 136 preliminary ? 2003 microchip technology inc. table 11-3: baud rates for asynchronous mode (brgh = 0 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3------- -- 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 high 1.221 - 255 0.977 - 255 0.610 - 255 low 312.500 - 0 250.000 - 0 156.250 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 - - - - - - 57.6 62.500 8.51 0 57.6 0 0 high 0.244 - 255 0.225 - 255 low 62.500 - 0 57.6 - 0 table 11-4: baud rates for asynchronous mode (brgh = 1 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3--------- 1.2--------- 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 high 4.883 - 255 3.906 - 255 2.441 - 255 low 1250.000 - 0 1000.000 0 625.000 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3------ 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 high 0.977 - 255 0.9 - 255 low 250.000 - 0 230.4 - 0
? 2003 microchip technology inc. preliminary ds30498b-page 137 pic16f7x7 table 11-5: intrc baud rates fo r asynchronous mode (brgh = 0 ) baud rate (k) f osc = 8 mhz f osc = 4 mhz f osc = 2 mhz f osc = 1 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na ? ? 0.300 0 207 0.300 0 103 0.300 0 51 1.2 1.202 +0.16 103 1.202 +0.16 51 1.202 +0.16 25 1.202 +0.16 12 2.4 2.404 +0.16 51 2.404 +0.16 25 2.404 +0.16 12 2.232 -6.99 6 9.6 9.615 +0.16 12 8.929 -6.99 6 10.417 +8.51 2 na ? ? 19.2 17.857 -6.99 6 20.833 +8.51 2 na ? ? na ? ? 28.8 31.250 +8.51 3 31.250 +8.51 1 31.250 +8.51 0 na ? ? 38.4 41.667 +8.51 2 na ? ? na ? ? na ? ? 57.6 62.500 +8.51 1 62.500 8.51 0 na ? ? na ? ? table 11-6: intrc baud rates fo r asynchronous mode (brgh = 1 ) baud rate (k) f osc = 8 mhz f osc = 4 mhz f osc = 2 mhz f osc = 1 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 na ? ? na ? ? na ? ? 0.300 0 207 1.2 na ? ? 1.202 +0.16 207 1.202 +0.16 103 1.202 +0.16 51 2.4 2.404 +0.16 207 2.404 +0.16 103 2.404 +0.16 51 2.404 +0.16 25 9.6 9.615 +0.16 51 9.615 +0.16 25 9.615 +0.16 12 8.929 -6.99 6 19.2 19.231 +0.16 25 19.231 +0.16 12 17.857 -6.99 6 20.833 +8.51 2 28.8 29.412 +2.12 16 27.778 -3.55 8 31.250 +8.51 3 31.250 +8.51 1 38.4 38.462 +0.16 12 35.714 -6.99 6 41.667 +8.51 2 na ? ? 57.6 55.556 -3.55 8 62.500 +8.51 3 62.500 +8.51 1 62.500 +8.51 0
pic16f7x7 ds30498b-page 138 preliminary ? 2003 microchip technology inc. 11.2 usart asynchronous mode in this mode, the usart uses standard non-return- to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip, dedicated, 8-bit baud rate gen- erator can be used to derive standard baud rate fre- quencies from the oscillator. the usart transmits and receives the lsb first. the transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit, sync (txsta<4>). the usart asynchronous module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 11.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit, txif (pir1<4>), is set. this inter- rupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr reg- ister. status bit trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit, txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 11-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 11-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to high-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg register can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 11-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ?
? 2003 microchip technology inc. preliminary ds30498b-page 139 pic16f7x7 when setting up an asynchronous transmission, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. figure 11-2: asynchronous master transmission figure 11-3: asynchronous master transmission (back to back) table 11-7: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows tw o consecutive transmissions.
pic16f7x7 ds30498b-page 140 preliminary ? 2003 microchip technology inc. 11.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 11-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit, cren (rcsta<4>). the heart of the receiver is the receive (serial) shift register (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit, rcie (pie1<5>). flag bit rcif is a read-only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double-buffered register (i.e., it is a two-deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, the overrun error bit, oerr (rcsta<1>), will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in soft- ware. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhib- ited and no further data will be received. it is, therefore, essential to clear error bit oerr if it is set. framing error bit, ferr (rcsta<2>), is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, therefore, it is essential for the user to read the rcsta register before reading the rcreg register, in order not to lose the old ferr and rx9d information. figure 11-4: usart receive block diagram figure 11-5: asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? f osc start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit bit 7/8 rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. bit stop bit start
? 2003 microchip technology inc. preliminary ds30498b-page 141 pic16f7x7 when setting up an asynchronous reception, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie is set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-8: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
pic16f7x7 ds30498b-page 142 preliminary ? 2003 microchip technology inc. 11.2.3 setting up 9-bit mode with address detect when setting up an asynchronous reception with address detect enabled: initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh. enable the asynchronous serial port by clearing bit sync and setting bit spen. if interrupts are desired, then set enable bit rcie. set bit rx9 to enable 9-bit reception. set adden to enable address detect. enable the reception by setting enable bit cren. flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. read the rcsta register to get the ninth bit and determine if any error occurred during reception. read the 8-bit received data by reading the rcreg register to determine if the device is being addressed. if any error occurred, clear the error by clearing enable bit cren. if the device has been addressed, clear the adden bit to allow data bytes and address bytes to be read into the receive buffer and interrupt the cpu. figure 11-6: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? rx9 adden rx9 adden rsr<8> enable load of receive buffer 8 8 f osc
? 2003 microchip technology inc. preliminary ds30498b-page 143 pic16f7x7 figure 11-7: asynchronous reception with address detect figure 11-8: asynchronous reception with address byte first table 11-9: registers associated with asynchronous reception start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 stop bit rc7/rx/dt (pin) load rsr read rcif word 1 rcreg bit 8 = 0 , data byte bit 8 = 1 , address byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden = 1 . start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 stop bit rc7/rx/dt (pin) load rsr read rcif word 1 rcreg bit 8 = 1 , address byte bit 8 = 0 , data byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden was not updated and still = 0 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
pic16f7x7 ds30498b-page 144 preliminary ? 2003 microchip technology inc. 11.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta<4>). in addition, enable bit, spen (rcsta<7>), is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit, csrc (txsta<7>). 11.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 11-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit, txif (pir1<4>), is set. the interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read- only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. transmission is enabled by setting enable bit, txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 11-9). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 11-10). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty so a transfer to the txreg register will result in an immediate transfer to tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to high- impedance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a high-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting since bit txen is still set. the dt line will immediately switch from high- impedance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?new? tx9d, the ?present? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set.
? 2003 microchip technology inc. preliminary ds30498b-page 145 pic16f7x7 table 11-10: registers associated with synchronous master transmission figure 11-9: synchronous transmission figure 11-10: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg = 0 . continuous transmission of two 8-bit words. pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
pic16f7x7 ds30498b-page 146 preliminary ? 2003 microchip technology inc. 11.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit, sren (rcsta<5>) or enable bit, cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit, rcie (pie1<5>). flag bit rcif is a read-only bit which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double-buffered register (i.e., it is a two- deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit, oerr (rcsta<1>), is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore, it is essential for the user to read the rcsta register before reading rcreg, in order not to lose the old rx9d information. when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 11.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-11: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. preliminary ds30498b-page 147 pic16f7x7 figure 11-11: synchronous reception (master mode, sren) cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brg = 0 . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4
pic16f7x7 ds30498b-page 148 preliminary ? 2003 microchip technology inc. 11.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit, csrc (txsta<7>). 11.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave transmission, follow these steps: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-12: registers associated with synchronous slave transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. preliminary ds30498b-page 149 pic16f7x7 11.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. bit sren is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr reg- ister will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave reception, follow these steps: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 11-13: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on 28-pin devices, always maintain these bits clear.
pic16f7x7 ds30498b-page 150 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 151 pic16f7x7 12.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 11 inputs for the pic16f737 and pic16f767 devices and 14 for the pic16f747 and pic16f777 devices. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. a new feature for the a/d converter is the addition of programmable acquisition time. this feature allows the user to select a new channel for conversion and to set the go/done bit immediately. when the go/done bit is set, the selected channel is sampled for the pro- grammed acquisition time before a conversion is actu- ally started. this removes the firmware overhead required to allow for an acquisition (sampling) period (see register 12-3 and section 12.2 ?selecting and configuring automatic acquisition time? ). the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 12-1, controls the operation of the a/d module and clock source. the adcon1 register, shown in register 12-2, configures the functions of the port pins, justification and voltage reference sources. the adcon2, shown in register 12-3, configures the programmed acquisition time. additional information on using the a/d module can be found in the picmicro ? mid-range mcu family reference manual (ds33023) and in application note an546, ?using the analog-to-digital (a/d) converter? (ds00546).
pic16f7x7 ds30498b-page 152 preliminary ? 2003 microchip technology inc. register 12-1: adcon0: a/d control register 0 (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits if adcs2 = 0 : 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (clock derived from an rc oscillation) if adcs2 = 1 : 00 = f osc /4 01 = f osc /16 10 = f osc /64 11 = f rc (clock derived from an rc oscillation) bit 5-3 chs<2:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) (1) 0110 = channel 06 (an6) (1) 0111 = channel 07 (an7) (1) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) 1101 = channel 13 (an13) 111x =unused note 1: selecting an5 through an7 on the 28-pin product variant (pic16f737 and pic16f767) will result in a full-scale conversion as unimplemented channels are connected to v dd . bit 2 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 1 chs<3>: analog channel select bit (see bit 5-3 for bit settings) bit 0 adon: a/d conversion status bit 1 = a/d converter module is operating 0 = a/d converter is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 153 pic16f7x7 register 12-2: adcon1: a/d control register 1 (address 9fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified. six most significant bits of adresh are read as ? 0 ?. 0 = left justified. six least significant bits of adresl are read as ? 0 ?. bit 6 adcs2: a/d clock divide by 2 select bit 1 = a/d clock source is divided by two when system clock is used 0 = disabled bit 5 vcfg1: voltage reference configuration bit 1 0 = v ref - is connected to v ss 1 = v ref - is connected to external v ref - (ra2) bit 4 vcfg0: voltage reference configuration bit 0 0 = v ref + is connected to v dd 1 = v ref + is connected to external v ref + (ra3) bit 3-0 pcfg<3:0>: a/d port configuration bits note: an5 through an7 are only available on the 40-pin product variant (pic16f747 and pic16f777). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a a a a aaaaaaaaaa 0001 a a a a aaaaaaaaaa 0010 d a a a aaaaaaaaaa 0011 d d a a aaaaaaaaaa 0100 d d d a aaaaaaaaaa 0101 d d d d aaaaaaaaaa 0110 d d d d daaaaaaaaa 0111 d d d d ddaaaaaaaa 1000 d d d d dddaaaaaaa 1001 d d d d dddd aaaaaa 1010 d d d d ddddd aaaaa 1011 d d d d ddddddaaaa 1100 d d d d dddddddaaa 1101 d d d d ddddddddaa 1110 d d d d ddddddddda 1111 d d d d dddddddddd legend: a = analog input, d = digital i/o
pic16f7x7 ds30498b-page 154 preliminary ? 2003 microchip technology inc. register 12-3: adcon2: a/d control register 2 the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ) or the voltage level on the ra3/an3/v ref + and ra2/an2/v ref -/cv ref pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 12-1. u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ? ? acqt2 acqt1 acqt0 ? ? ? bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-3 acqt<2:0>: a/d acquisition time select bits 000 =0 (1) 001 =2 t ad 010 =4 t ad 011 =6 t ad 100 =8 t ad 101 =12t ad 110 =16 t ad 111 =20 t ad note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. bit 2-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 155 pic16f7x7 the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/ adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 12.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set peie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 12-1: a/d block diagram (input voltage) v in v ref + (reference voltage) v dd vcfg<1:0> chs<3:0> an3/v ref + an2/v ref - an1 an0 0011 0010 0001 0000 a/d converter v ref - (reference voltage) v ss vcfg<1:0> an12 an13 an11 1101 1100 1011 s s
pic16f7x7 ds30498b-page 156 preliminary ? 2003 microchip technology inc. 12.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 12-2. the maximum recom- mended impedance for analog sources is 2.5 k ? . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range mcu family reference manual (ds33023). equation 12-1: acquisition time figure 12-2: analog input model t acq t c t acq = = = = = = = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff 2 s + t c + [(temperature -25 c)(0.05 s/c)] c hold (r ic + r ss + r s ) in(1/2047) -120 pf (1 k ? + 7 k ? + 10 k ? ) in(0.0004885) 16.47 s 2 s + 16.47 s + [(50c ? 25 c)(0.05 s/ c) 19.72 s note 1: the reference voltage (v ref ) has no effect on the equation since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. 4: after a conversion has completed, a 2.0 t ad delay must complete before acquisition can begin again. during this time, the holding capacitor is not connected to the selected a/d input channel. c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 2003 microchip technology inc. preliminary ds30498b-page 157 pic16f7x7 12.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state (? 000 ?) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a pro- grammable acquisition time for the a/d module. when the go/done bit is set, the a/d module continues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisi- tion time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 12.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires a minimum 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selected. the seven possible options for t ad are: 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal a/d module, rc oscillator (2-6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 12-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 12-1: t ad vs. maximum device operating frequencies (standard devices (f)) ad clock source (t ad ) maximum device frequency operation adcs2:adcs1:adcs0 max. 2 t osc 000 1.25 mhz 4 t osc 100 2.5 mhz 8 t osc 001 5 mhz 16 t osc 101 10 mhz 32 t osc 010 20 mhz 64 t osc 110 20 mhz rc (1, 2, 3) x11 (note 1) note 1: the rc source has a typical t ad time of 4 s but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lf), please refer to section 18.0 ?electrical characteristics? .
pic16f7x7 ds30498b-page 158 preliminary ? 2003 microchip technology inc. 12.4 operation in power managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power managed mode. if the a/d is expected to operate while the device is in a power managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the power managed mode clock that will be used. after the power managed mode is entered (either of the power managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power managed mode clock source until the conversion has been completed. if the power managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d rc clock to be selected. if bits acqt2:acqt0 are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. 12.5 configuring analog port pins the adcon1, trisa, trisb and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their cor- responding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally config- ured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the digital input buffer to con- sume current that is out of the device?s specification.
? 2003 microchip technology inc. preliminary ds30498b-page 159 pic16f7x7 12.6 a/d conversions figure 12-3 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the follow- ing instruction to allow entry into sleep mode before the conversion begins. figure 12-4 shows the operation of the a/d converter after the go bit has been set, the acqt2:acqt0 bits are set to ? 010 ? and a 4 t ad acquisition time is selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. figure 12-3: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 12-4: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7
pic16f7x7 ds30498b-page 160 preliminary ? 2003 microchip technology inc. 12.7 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 12.8 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all a/ d input pins are configured as analog inputs. the adres register will contain unknown data after a power-on reset. 12.9 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and an appropriate acquisi- tion time should pass before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module but will still reset the timer1 counter. table 12-2: summary of a/d registers note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 osfif cmif lvdif ?bclif ? ccp3if ccp2if 000- 0-00 000- 0-00 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 osfie cmie lvdie ?bclie ? ccp3ie ccp2ie 000- 0--0 000- 0--0 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 9fh adcon1 adfm adcs2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 000 0000 0000 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 uu0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 09h porte (2) ? ? ? ? ?re2re1re0 ---- x000 ---- x000 89h trise (2) ibf obf ibov pspmode ? (3) porte data direction bits 0000 1111 0000 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic16f737/767 devices; always maintain these bits clear. 2: these registers are reserv ed on the pic16f737/767 devices. 3: re3 is an input only. the state of the trise3 bit has no effect and will always read ? 1 ?.
? 2003 microchip technology inc. preliminary ds30498b-page 161 pic16f7x7 13.0 comparator module the comparator module contains two analog com- parators. the inputs to the comparators are multiplexed with i/o port pins ra0 through ra3, while the outputs are multiplexed to pins ra4 and ra5. the on-chip voltage reference ( section 14.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register (register 13-1) controls the com- parator input and output multiplexers. a block diagram of the various comparator configurations is shown in figure 13-1. register 13-1: cmcon register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to ra3/an3 c2 v in - connects to ra2/an2 0 =c1 v in - connects to ra0/an0 c2 v in - connects to ra1/an1 bit 2-0 cm2:cm0 : comparator mode bits figure 13-1 shows the comparator modes and cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 162 preliminary ? 2003 microchip technology inc. 13.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 13-1 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in the electrical specifications ( section 18.0 ?electrical characteristics? ). figure 13-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change. otherwise, a false interrupt may occur. c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators reset a a cm2:cm0 = 000 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) a a c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators a a cm2:cm0 = 010 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators a a cm2:cm0 = 100 c2 ra1/an1 v in - v in + ra2/an2 c2out a d c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 ra0/an0 v in - v in + ra3/an3 c1out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators off (por default mode) d d cm2:cm0 = 111 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ? ) d d c1 ra0/an0 v in - v in + ra3/an3 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 ra1/an1 v in - v in + ra2/an2 c2out a a from comparator cis = 0 cis = 1 cis = 0 cis = 1 c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 ra1/an1 v in - v in + ra2/an2 c2out a d a = analog input, port reads zeros always d = digital i nput cis (cmcon<3>) is the comparator input switch cv ref c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 ra1/an1 v in - v in + ra2/an2 c2out a a ra4/t0cki/c1out ra5/an4/lvdin/ss /c2out ra4/t0cki/c1out ra5/an4/lvdin/ss /c2out ra4/t0cki/c1out v ref module
? 2003 microchip technology inc. preliminary ds30498b-page 163 pic16f7x7 13.2 comparator operation a single comparator is shown in figure 13-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 13-2 represent the uncertainty due to input offsets and response time. 13.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 13-2). figure 13-2: single comparator 13.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 13.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the compara- tors. section 14.0 ?comparator voltage reference module? contains a detailed description of the compar- ator voltage reference module that provides this signal. the internal reference signal is used when comparators are in mode cm<2:0> = 110 (figure 13-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 13.4 comparator response time response time is the minimum time after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal reference is changed, the maximum delay of the inter- nal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used ( section 18.0 ?electrical characteristics? ). 13.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the ra4 and ra5 i/o pins. when enabled, multiplexors in the output path of the ra4 and ra5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 13-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra4 and ra5 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in - output v in? v in+ o utput output v in + v in - note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume more current than is specified. 3: ra4 is an open collector i/o pin. when used as an output, a pull-up resistor is required.
pic16f7x7 ds30498b-page 164 preliminary ? 2003 microchip technology inc. figure 13-3: comparator output block diagram 13.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit must be reset by clearing it (? 0 ?). since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. d q en to ra4 or ra5 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon r eset from other comparator cxinv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2003 microchip technology inc. preliminary ds30498b-page 165 pic16f7x7 13.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current as shown in the com- parator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm<2:0> = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 13.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator off mode, cm<2:0> = 111 . this ensures compatibility to the pic16f87x devices. 13.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 13-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 13-4: analog input model table 13-1: registers associated with comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u 0dh pir2 osfif cmif lvdif ? bclif ? ccp3if ccp2if 000- 0-00 000- 0-00 8dh pie2 osfie cmie lvdie ? bclie ? ccp3ie ccp2ie 000- 0-00 000- 0-00 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 uu0u 0000 85h trisa trisa7 trisa6 porta data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module. va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage
pic16f7x7 ds30498b-page 166 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 167 pic16f7x7 14.0 comparator voltage reference module the comparator voltage reference generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ? 110 ?. a programmable register controls the function of the reference generator. register 14-1 lists the bit functions of the cvrcon register. as shown in figure 14-1, the resistor ladder is seg- mented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the comparator reference supply voltage (also referred to as cv rsrc ) comes directly from v dd . it should be noted, however, that the voltage at the top of the ladder is cv rsrc ? v sat , where v sat is the saturation voltage of the power switch transistor. this reference will only be as accurate as the values of cv rsrc and v sat . the output of the reference generator may be connected to the ra2/an2/v ref -/cv ref pin. this can be used as a simple d/a function by the user if a very high-impedance load is used. the primary purpose of this function is to provide a test path for testing the reference generator function. register 14-1: cvrcon control register (address 9dh) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 = cv ref circuit powered on 0 = cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 = cv ref voltage level is output on ra2/an2/v ref -/cv ref pin 0 = cv ref voltage level is disconnected from ra2/an2/v ref -/cv ref pin bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.75 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 unimplemented: read as ? 0 ? bit 3-0 cvr3:cvr0: comparator v ref value selection bits 0 vr3:vr0 15 when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr3:cvr0/32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 168 preliminary ? 2003 microchip technology inc. figure 14-1: comparator voltage reference block diagram table 14-1: registers associated with comparator voltage reference cvrr 8r cvr3 cvr0 16:1 analog mux 8r r r r r cvren cv ref 16 stages input to comparator cvroe ra2/an2/v ref -/cv ref v dd cvr2 cvr1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference.
? 2003 microchip technology inc. preliminary ds30498b-page 169 pic16f7x7 15.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection: reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) - low-voltage detect (lvd) interrupts watchdog timer (wdt) two-speed start-up fail-safe clock monitor sleep code protection id locations in-circuit serial programming there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscil- lator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes and is enabled or disabled using a configuration bit. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. configuration bits are used to select the desired oscillator mode. additional information on special features is available in the picmicro ? mid-range mcu family reference manual (ds33023). 15.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these bits are mapped in program memory locations 2007h and 2008h. the user will note that address 2007h is beyond the user program memory space which can be accessed only during programming.
pic16f7x7 ds30498b-page 170 preliminary ? 2003 microchip technology inc. register 15-1: configuration word register 1 (address 2007h) r/p-1 r/p-1 r/p-1 u-1 u-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp ccpmx debug ? ? borv1 borv0 boren mclre f osc 2pwrten wdten f osc 1f osc 0 bit 13 bit 0 bit 13 cp: flash program memory code protection bits 1 = code protection off 0 = 0000h to 1fffh code-protected for pic16f767/777 an d 0000h to 0fffh for pic16f737/747 (all protected) bit 12 ccpmx: ccp2 multiplex bit 1 = ccp2 is on rc1 0 = ccp2 is on rb3 bit 11 debug: in-circuit debugger mode bit 1 = in-circuit debugger disabled, rb6 and rb7 are general purpose i/o pins 0 = in-circuit debugger enabled, rb6 and rb7 are dedicated to the debugger bit 10-9 unimplemented: read as ? 1 ? bit 8-7 borv<1:0>: brown-out reset voltage bits 11 = v bor set to 2.0v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 6 boren: brown-out reset enable bit boren combines with borsen to control when bor is enabled and how it is controlled. boren:borsen: 11 = bor enabled and always on 10 = bor enabled during operation and disabled during sleep by hardware 01 = bor controlled by software bit sboren (refer to pcon register (register 2-8), bit 2) 00 = bor disabled bit 5 mclre: mclr /v pp /re3 pin function select bit 1 = mclr /v pp /re3 pin function is mclr 0 = mclr /v pp /re3 pin function is digital input only, mclr gated to ? 1 ? bit 3 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 4, 1-0 f osc 2:f osc 0: oscillator selection bits 111 = extrc oscillator; clko function on osc2/clko/ra6 110 = extrc oscillator; port i/o function on osc2/clko/ra6 101 = intrc oscillator; clko function on osc2/clk o/ra6 and port i/o function on osc1/clki/ra7 100 = intrc oscillator; port i/o function on osc1/clki/ra7 and osc2/clko/ra6 011 = extclk; port i/o function on osc2/clko/ra6 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 171 pic16f7x7 register 15-2: configuration word register 2 (address 2008h) u-1 u-1 u-1 u-1 u-1 u-1 u-1 r/p-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 ? ? ? ? ? ? ? borsen ? ? ? ? ieso fcmen bit 13 bit 0 bit 13-7 unimplemented: read as ? 1 ? bit 6 borsen: brown-out reset software enable bit refer to configuration word register 1, bit 6 for the function of this bit. bit 5-2 unimplemented: read as ? 1 ? bit 1 ieso: internal external switch over bit 1 = internal external switch over mode enabled 0 = internal external switch over mode disabled bit 0 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f7x7 ds30498b-page 172 preliminary ? 2003 microchip technology inc. 15.2 reset the pic16f7x7 differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset during normal operation wdt wake-up during sleep brown-out reset (bor) some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep and brown- out reset (bor). they are not affected by a wdt wake-up which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differ- ently in different reset situations, as indicated in table 15-3. these bits are used in software to deter- mine the nature of the reset. upon a por, bor or wake-up from sleep, the cpu requires approximately 5-10 s to become ready for code execution. this delay runs in parallel with any other timers. see table 15-4 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 15-1. figure 15-1: simplified block diagram of on-chip reset circuit s r q external reset mclr /v pp /re3 pin v dd osc1/ wdt module v dd rise detect ost/pwrt intrc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt sleep brown-out detect borsen boren clki pin note 1: this is the 32 khz intrc oscillator. see section 4.0 ?oscillator configurations? for more information.
? 2003 microchip technology inc. preliminary ds30498b-page 173 pic16f7x7 15.3 mclr pic16f7x7 devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from previous devices of this family. voltages applied to the pin that exceed its specification can result in both mclr and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 15-2, is suggested. the mclr /v pp /re3 pin can be configured for mclr (default) or as an input pin (re3). this is configured through the mclre bit in configuration word register 1. figure 15-2: recommended mclr circuit 15.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v-1.7v). to take advantage of the por, tie the mclr pin to v dd , as described in section 15.3 ?mclr? . a maximum rise time for v dd is specified. see section 18.0 ?electrical characteristics? for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for more information, see application note an607, ?power-up trouble shooting? (ds00607). 15.5 power-up timer (pwrt) the power-up timer (pwrt) of the pic16f7x7 is a counter that uses the intrc oscillator as the clock input. this yields a count of 72 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc and will vary from chip-to-chip due to temperature and process variation. see dc parameter #33 for details. the pwrt is enabled by clearing configuration bit pwrten . 15.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycles (from osc1 input) delay after the pwrt delay is over (if enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 15.7 brown-out reset (bor) three configuration bits (boren ? configuration word register 1, bit 6; borsen ? configuration word reg- ister 2, bit 6; sboren ? pcon, bit 2) together disable or enable the brown-out reset circuit in one of its three operating modes. if v dd falls below v bor (defined by borv<1:0> bits in configuration word register 1) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer (if enabled) will keep the device in reset for t pwrt (parameter #33, about 72 ms). if v dd should fall below v bor during t pwrt , the brown-out reset process will restart when v dd rises above v bor with the power-up timer reset. unlike previous pic16 devices, the pwrt is no longer automatically enabled when the brown-out reset circuit is enabled. the pwrten and boren configuration bits are independent of each other. c1 0.1 f r1 1 k ? (or greater) (optional, not critical) v dd mclr pic16f7x7
pic16f7x7 ds30498b-page 174 preliminary ? 2003 microchip technology inc. 15.8 low-voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do ?housekeeping tasks? before the device voltage exits the valid operating range. this can be done using the low-voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low-voltage detect circuitry is completely under software control. this allows the circuitry to be turned off by the software which minimizes the current consumption for the device. figure 15-3 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference, t b ? t a , is the total time for shutdown. the block diagram for the lvd module is shown in figure 15-4. a comparator uses an internally gener- ated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a ?trip point? voltage. the ?trip point? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2v internal reference voltage generated by the voltage ref- erence module. the comparator then generates an interrupt signal setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 15-4). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 15-3: typical low-voltage detect application time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend:
? 2003 microchip technology inc. preliminary ds30498b-page 175 pic16f7x7 figure 15-4: low-voltage detect (lvd) block diagram the lvd module has an additional feature that allows the user to supply the sense voltage to the module from an external source. this mode is enabled when bits lvdl3:lvdl0 are set to ? 1111 ?. in this state, the comparator input is multiplexed from the external input pin, lvdin (figure 15-5). this gives users flexibility because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 15-5: low-voltage detect (lvd) with external input block diagram lvdif v dd 16 to 1 mux lvden lvd control register internally generated reference voltage lvdin 1.2v lvd en lvd control 16 to 1 mux bgap boden lvden vxen lvdin register v dd v dd externally generated trip point
pic16f7x7 ds30498b-page 176 preliminary ? 2003 microchip technology inc. 15.9 control register the low-voltage detect control register controls the operation of the low-voltage detect circuitry. register 15-3: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low-voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low-voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low-voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low-voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.50v-4.78v 1101 = 4.20v-4.46v 1100 = 4.00v-4.26v 1011 = 3.80v-4.04v 1010 = 3.60v-3.84v 1001 = 3.50v-3.72v 1000 = 3.30v-3.52v 0111 = 3.00v-3.20v 0110 = 2.80v-2.98v 0101 = 2.70v-2.86v 0100 = 2.50v-2.66v 0011 = 2.40v-2.55v 0010 = 2.20v-2.34v 0001 = reserved 0000 = reserved note: lvdl3:lvdl0 modes which result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. preliminary ds30498b-page 177 pic16f7x7 15.10 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be con- stantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register) which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 15-6 shows typical waveforms that the lvd module may be used to detect. figure 15-6: low-voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated t ivrst lvdif may not be set enable lvd lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable t ivrst
pic16f7x7 ds30498b-page 178 preliminary ? 2003 microchip technology inc. 15.10.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 15-6. 15.10.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 15.11 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 15.12 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off. 15.13 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, all delays will expire. bringing mclr high will begin execution immediately. this is useful for testing purposes or to synchronize more than one pic16f7x7 device operating in parallel. table 15-3 shows the reset conditions for the status, pcon and pc registers, while table 15-4 shows the reset conditions for all the registers. 15.14 power control/status register (pcon) the power control/status register, pcon, has two bits to indicate the type of reset that last occurred. bit 0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a brown-out reset occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable. bit 1 is power-on reset status bit, por . it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. note: if the lvd is enabled and the bor module is not enabled, the band gap will require a start-up time of no more than 50 s before the band gap reference is stable. before enabling the lvd interrupt, the user should ensure that the band gap reference voltage is stable by monitoring the irvst bit in the lvdcon register. the lvd could cause erroneous interrupts before the band gap is stable.
? 2003 microchip technology inc. preliminary ds30498b-page 179 pic16f7x7 table 15-1: time-out in various situations table 15-2: status bits and their significance table 15-3: reset condition for special registers oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024 t osc 1024 t osc t pwrt + 1024 t osc 1024 t osc 1024 t osc extrc, intrc t pwrt 5-10 s (1) t pwrt 5-10 s (1) 5-10 s (1) t1osc ? ???5-10 s (1) note 1: cpu start-up is always invoked on por, bor and wake-up from sleep. the 5 s-10 s delay is based on a 1 mhz system clock. por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep legend: u = unchanged, x = unknown condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16f7x7 ds30498b-page 180 preliminary ? 2003 microchip technology inc. table 15-4: initialization conditions for all registers register power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta xx0x 0000 uu0u 0000 uuuu uuuu portb xx00 0000 uu00 0000 uuuu uuuu portc xxxx xxxx uuuu uuuu uuuu uuuu portd xxxx xxxx uuuu uuuu uuuu uuuu porte (pic16f737/767) porte (pic16f747/777) ---- x--- ---- x000 ---- u--- ---- u000 ---- u--- ---- uuuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 0000 0000 0000 0000 uuuu uuuu (1) pir2 000- 0-00 000- 0-00 uuu- u-uu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con -000 0000 -uuu uuuu -uuu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu sspcon2 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu ccp2con --00 0000 --00 0000 --uu uuuu ccp3con --00 0000 --00 0000 uuuu uuuu ccpr2l xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h xxxx xxxx uuuu uuuu uuuu uuuu ccpr3l xxxx xxxx uuuu uuuu uuuu uuuu ccpr3h xxxx xxxx uuuu uuuu uuuu uuuu rcsta 0000 000x 0000 000x uuuu uuuu txreg 0000 0000 0000 0000 uuuu uuuu rcreg 0000 0000 0000 0000 uuuu uuuu adresh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 0000 0000 0000 uuuu uuuu option 1111 1111 1111 1111 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and pr2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 15-3 for reset value for specific condition.
? 2003 microchip technology inc. preliminary ds30498b-page 181 pic16f7x7 trisa 1111 1111 1111 1111 uuuu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 1111 1111 1111 1111 uuuu uuuu trisd 1111 1111 1111 1111 uuuu uuuu trise (pic16f737/767) trise (pic16f747/777) ---- 1--- 0000 1111 ---- u--- 0000 1111 ---- 1--- uuuu uuuu pie1 0000 0000 0000 0000 -uuu uuuu pie2 000- 0-00 000- 0-00 uuu- u-uu pcon ---- -1qq ---- -uuu ---- -uuu osccon -000 1000 -000 1000 -uuu uuuu osctune --00 0000 --00 0000 --uu uuuu pr2 1111 1111 1111 1111 1111 1111 sspadd 0000 0000 0000 0000 uuuu uuuu sspstat 0000 0000 0000 0000 uuuu uuuu txsta 0000 -010 0000 -010 uuuu -u1u spbrg 0000 0000 0000 0000 uuuu uuuu cmcon 0000 0111 0000 0111 uuuu uuuu cvrcon 000- 0000 000- 0000 uuu- uuuu wdtcon ---0 1000 ---0 1000 ---u uuuu adresl xxxx xxxx uuuu uuuu uuuu uuuu adcon1 0000 0000 0000 0000 uuuu uuuu adcon2 --00 0--- --00 0--- uuuu uuuu pmdata xxxx xxxx uuuu uuuu uuuu uuuu pmadr xxxx xxxx uuuu uuuu uuuu uuuu pmdath --xx xxxx --uu uuuu --uu uuuu pmadrh ---- xxxx ---- uuuu ---- uuuu pmcon1 ---- ---0 ---- ---u ---- ---u lvdcon --00 0101 --00 0101 --uu uuuu table 15-4: initialization conditi ons for all registers (continued) register power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear note 1: one or more bits in intcon, pir1 and pr2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 15-3 for reset value for specific condition.
pic16f7x7 ds30498b-page 182 preliminary ? 2003 microchip technology inc. figure 15-7: time-out sequence on power-up (mclr tied to v dd through pull-up resistor) figure 15-8: time-out sequence on power-up (mclr tied to v dd through rc network): case 1 figure 15-9: time-out sequence on power-up (mclr tied to v dd through rc network): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2003 microchip technology inc. preliminary ds30498b-page 183 pic16f7x7 figure 15-10: slow rise time (mclr tied to v dd through rc network) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
pic16f7x7 ds30498b-page 184 preliminary ? 2003 microchip technology inc. 15.15 interrupts the pic16f7x7 has up to 17 sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. when bit gie is enabled and an interrupt?s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be disabled through their corresponding enable bits in various registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine, as well as sets the gie bit which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the special function register, pir1. the corresponding interrupt enable bits are contained in special function register, pie1 and the peripheral interrupt enable bit is contained in special function register, intcon. when an interrupt is serviced, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends on when the interrupt event occurs relative to the current q cycle. the latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit, peie bit or the gie bit. figure 15-11: interrupt logic note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. osfif osfie adif adie rcif rcie txif txie sspif sspie tmr2if tmr2ie tmr1if tmr1ie tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu pspif (1) pspie (1) ccp1if ccp1ie cmie cmif bclif bclie ccp3if ccp3ie ccp2if ccp2ie note 1: psp interrupt is implemented only on pic16f747/777 devices.
? 2003 microchip technology inc. preliminary ds30498b-page 185 pic16f7x7 15.15.1 int interrupt external interrupt on the rb0/int pin is edge-triggered, either rising if bit intedg (option<6>) is set or falling if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit, inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re- enabling this interrupt. the int interrupt can wake-up the processor from sleep if bit inte was set prior to going into sleep. the status of global interrupt enable bit, gie, decides whether or not the processor branches to the interrupt vector following wake-up. see section 15.18 ?power-down mode (sleep)? for details on sleep mode. 15.15.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit, tmr0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>), see section 6.0 ?timer0 module? . 15.15.3 portb intcon change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<4>), see section 2.2 ?data memory organization? . 15.16 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (i.e., w, status registers). since the upper 16 bytes of each bank are common in the pic16f7x7 devices, temporary holding registers w_temp, status_temp and pclath_temp should be placed in here. these 16 locations don?t require banking and therefore, make it easier for con- text save and restore. the same code shown in example 15-1 can be used. example 15-1: saving status and w registers in ram movwf w_temp ;copy w to temp register swapf status, w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp, w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp, f ;swap w_temp swapf w_temp, w ;swap w_temp into w
pic16f7x7 ds30498b-page 186 preliminary ? 2003 microchip technology inc. 15.17 watchdog timer (wdt) for pic16f7x7 devices, the wdt has been modified from previous pic16 devices. the new wdt is code and functionally backward compatible with previous pic16 wdt modules, and allows the user to have a scaler value for the wdt and tmr0 at the same time. in addition, the wdt time-out value can be extended to 268 seconds, using the prescaler with the postscaler when psa is set to ? 1 ?. 15.17.1 wdt oscillator the wdt derives its time base from the 31.25 khz intrc; therefore, the accuracy of the 31.25 khz will be the same accuracy for the wdt time-out period. the value of wdtcon is ? ---0 1000 ? on all resets. this gives a nominal time base of 16.38 ms, which is compatible with the time base generated with previous pic16 microcontroller versions. a new prescaler has been added to the path between the internal rc and the multiplexors used to select the path for the wdt. this prescaler is 16 bits and can be programmed to divide the internal rc by 128 to 65536, giving the time base used for the wdt a nominal range of 1 ms to 2.097s. 15.17.2 wdt control the wdten bit is located in configuration word register 1 and when this bit is set, the wdt runs continuously. the swdten bit is in the wdtcon register. when the wdten bit in the configuration word register 1 is set, the swdten bit has no effect. if wdten is clear, then the swdten bit can be used to enable and disable the wdt. setting the bit will enable it and clearing the bit will disable it. the psa and ps<2:0> bits (option_reg) have the same function as in previous versions of the pic16 family of microcontrollers. figure 15-12: watchdo g timer block diagram note: when the ost is invoked, the wdt is held in reset because the wdt ripple counter is used by the ost to perform the oscilla- tor delay count. when the ost count has expired, the wdt will begin counting (if enabled). table 15-5: prescaler/postscaler bit status conditions prescaler postscaler (psa = 1 ) wdten = 0 cleared cleared clrwdt command osc fail detected exit sleep + system clock = t1osc, extrc, intrc, extclk exit sleep + system clock = xt, hs, lp cleared at end of ost cleared at end of ost 31.25 khz psa 16-bit programmable prescaler wdt from tmr0 clock source postscaler 8 ps<2:0> psa wdt time-out to tmr0 wdtps<3:0> wdten from configuration word 1 1 0 0 swdten from wdtcon intrc clock
? 2003 microchip technology inc. preliminary ds30498b-page 187 pic16f7x7 register 15-4: wdtcon register table 15-6: summary of watchdog timer registers u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps<3:0>: watchdog timer period select bits 0000 = 1:32 prescale rate 0001 = 1:64 prescale rate 0010 = 1:128 prescale rate 0011 = 1:256 prescale rate 0100 = 1:512 prescale rate 0101 = 1:1024 prescale rate 0110 = 1:2048 prescale rate 0111 = 1:4096 prescale rate 1000 = 1:8192 prescale rate 1001 = 1:16394 prescale rate 1010 = 1:32768 prescale rate 1011 = 1:65536 prescale rate 1100 = 1:1 prescale rate bit 0 swdten: software enable/disable for watchdog timer bit (1) 1 = wdt is turned on 0 = wdt is turned off note 1: if wdten configuration bit = 1 , then wdt is always enabled irrespective of this control bit. if wdten configuration bit = 0 , then it is possible to turn wdt on/off with this control bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 2007h configuration bits borv0 boren mclre f osc 2 pwrten wdten f osc 1 f osc 0 uuuu uuuu uuuu uuuu 105h wdtcon ? ? ? wdtps3 wdtps2 wstps1 wdtps0 swdten ---0 1000 ---0 1000 legend: shaded cells are not used by the watchdog timer. note 1: see register 15-1 for operation of these bits.
pic16f7x7 ds30498b-page 188 preliminary ? 2003 microchip technology inc. 15.17.3 two-speed clock start-up mode two-speed start-up minimizes the latency between oscillator start-up and code execution that may be selected with the ieso (internal/external switch over) bit in configuration word register 2. this mode is achieved by initially using the intrc for code execution until the primary oscillator is stable. if this mode is enabled and any of the following condi- tions exist, the system will begin execution with the intrc oscillator. this results in almost immediate code execution with a minimum of delay. por and after the power-up timer has expired (if pwrten = 0 ) or following a wake-up from sleep or a reset, when running from t1osc or intrc (after a reset, scs<1:0> are always set to ? 00 ?). if the primary oscillator is configured to be anything other than xt, lp or hs, then two-speed start-up is disabled because the primary oscillator will not require any time to become stable after por or an exit from sleep. if the ircf bits of the osccon register are configured to a non-zero value prior to entering sleep mode, the secondary system clock frequency will come from the output of the intosc. the iofs bit in the osccon register will be clear until the intosc is stable. this will allow the user to determine when the internal oscillator can be used for time critical applications. checking the state of the osts bit will confirm whether the primary clock configuration is engaged. if not, the osts bit will remain clear. when the device is auto-configured in intrc mode following a por or wake-up from sleep, the rules for entering other oscillator modes still apply, meaning the scs<1:0> bits in osccon can be modified before the ost time-out has occurred. this would allow the application to wake-up from sleep, perform a few instructions using the intrc as the clock source and go back to sleep without waiting for the primary oscillator to become stable. 15.17.3.1 two-speed start-up sequence 1. wake-up from sleep, reset or por. 2. oscon bits configured to run from intrc (31.25 khz). 3. instructions begin execution by intrc (31.25 khz). 4. ost enabled to count 1024 clock cycles. 5. ost timed out, wait for falling edge of intrc. 6. osts is set. 7. system clock held low for eight falling edges of new clock (lp, xt or hs). 8. system clock is switched to primary source (lp, xt or hs). the software may read the osts bit to determine when the switch over takes place so that any software timing edges can be adjusted. figure 15-13: two-speed start-up note: following any reset, the ircf bits are zeroed and the frequency selection is forced to 31.25 khz. the user can modify the ircf bits to select a higher internal oscillator frequency. note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit to remain clear. q4 q1 q3 q4 q1 q2 osc1 sleep program pc 0000h intrc t ost q3 q4 osc2 osts system clock 0001h q1 q2 q3 q4 q1 q2 counter 0004h 0005h 0003h q1 q2 q3 q4 cpu start-up
? 2003 microchip technology inc. preliminary ds30498b-page 189 pic16f7x7 15.17.4 fail-safe option the fail-safe clock monitor (fscm) is designed to allow the device to continue to operate even in the event of an oscillator failure. figure 15-14: fscm block diagram the fscm function is enabled by setting the fcmen bit in configuration word register 2. in the event of an oscillator failure, the fscm will generate an oscillator fail interrupt and will switch the system clock over to the internal oscillator. the system will continue to come from the internal oscillator until the fail-safe condition is exited. the fail-safe condition is exited with either a reset, the execution of a sleep instruction or a write to the scs bits of a different value. the frequency of the internal oscillator will depend upon the value contained in the ircf bits. another clock source can be selected via the ircf and the scs bits of the osccon register. the fscm sample clock is generated by dividing the intrc clock by 64. this will allow enough time between fscm sample clocks for a system clock edge to occur. on the rising edge of the postscaled clock, the monitoring latch (cm = 0 ) will be cleared. on a falling edge of the primary or secondary system clock, the monitoring latch will be set (cm = 1 ). in the event that a falling edge of the postscaled clock occurs and the monitoring latch is not set, a clock failure has been detected. while in fail-safe mode, a reset will exit the fail-safe condition. if the primary clock source is configured for a crystal, the ost timer will wait for the 1024 clock cycles for the ost time-out and the device will con- tinue running from the internal oscillator until the ost is complete. a sleep instruction, or a write to the scs bits (where scs bits do not = 00 ), can be performed to put the device into a low-power mode. if reset occurs while in fail-safe mode and the primary clock source is ec or rc, then the device will immediately switch back to ec or rc mode. 15.17.4.1 fail-safe in low-power mode a change of scs<1:0> or the sleep instruction will end the fail-safe condition. the system clock will default to the source selected by the scs bits, which is either t1osc, intrc or none (sleep mode). how- ever, the fscm will continue to monitor the system clock. if the secondary clock fails, the device will immediately switch to the internal oscillator clock. if osfie is set, an interrupt will be generated. figure 15-15: fscm timing diagram peripheral intrc 64 s c q 31.25 khz (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected oscillator clock q note: two-speed start-up is automatically enabled when the fail-safe option is enabled. oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test
pic16f7x7 ds30498b-page 190 preliminary ? 2003 microchip technology inc. 15.17.4.2 fscm and the watchdog timer when a clock failure is detected, scs<1:0> will be forced to ? 10 ? which will reset the wdt (if enabled). 15.17.4.3 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary system clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, lp or xt), the situation is somewhat different. since the oscillator may require a start-up time consid- erably longer than the fscm sample clock time, a false clock failure may be detected. to prevent this, the inter- nal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intr returns to its role as the fscm source. 15.18 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or high-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for low- est current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 15.18.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ?wake-up?. the to and pd bits in the status register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. a/d conversion (when a/d clock source is rc). 7. eeprom write operation completion. 8. comparator output changes state. 9. usart rx or tx (synchronous slave mode). other peripherals cannot generate interrupts since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execu- tion of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. note: the same logic that prevents false oscilla- tor failure interrupts on por or wake from sleep, will also prevent the detection of the oscillator?s failure to start at all follow- ing these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged.
? 2003 microchip technology inc. preliminary ds30498b-page 191 pic16f7x7 15.18.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt prescaler and postscaler (if enabled) will not be cleared, the to bit will not be set and the pd bit will not be cleared. if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt prescaler and postscaler (if enabled) will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. figure 15-16: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale). this delay will not be there for rc osc mode. 3: gie = 1 assumed. in this case, after wake-up, th e processor jumps to the interrupt routine. if gie = 0 , execution will continue in-line. 4: clko is not available in these osc modes but shown here for timing reference.
pic16f7x7 ds30498b-page 192 preliminary ? 2003 microchip technology inc. 15.19 in-circuit debugger when the debug bit in the configuration word is pro- grammed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? icd. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 15-7 shows which features are consumed by the background debugger. table 15-7: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debugger module available from microchip, or one of the third party development tool companies. 15.20 program verification/code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 15.21 id locations four memory locations (2000h-2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. it is recommended that only the four least significant bits of the id location are used. 15.22 in-circuit serial programming pic16f7x7 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage (see figure 15-17 for an example). this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. for general information of serial programming, please refer to the in-circuit serial programming? (icsp?) guide (ds30277). figure 15-17: typical in-circuit serial programming connection i/o pins rb6, rb7 stack 1 level program memory address 0000h must be nop last 100h words data memory 0x070 (0x0f0, 0x170, 0x1f0) 0x1eb-0x1ef external connector signals to n o r m a l connections to n o rm a l connections pic16f7x7 v dd v ss mclr /v pp /re3 rb6 rb7 +5v 0v v pp clk data i/o v dd * * * * * isolation devices (as required).
? 2003 microchip technology inc. preliminary ds30498b-page 193 pic16f7x7 16.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories: byte-oriented operations bit-oriented operations literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the formats for each of the categories are presented in figure 16-1, while the various opcode fields are summarized in table 16-1. table 13-2 lists the instructions recognized by the mpasm tm assembler. a complete description of each instruction is also available in the picmicro ? mid-range mcu family reference manual (ds33023). for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the bit affected by the opera- tion, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an eight or eleven-bit constant or literal value one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 16.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a ? clrf portb ? instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unin- tended result that the condition that sets the rbif flag would be cleared for pins configured as inputs and using the portb interrupt-on-change feature. table 16-1: opcode field descriptions figure 16-1: general format for instructions note: to maintain upward compatibility with future pic16f7x7 products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1 . pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f7x7 ds30498b-page 194 preliminary ? 2003 microchip technology inc. table 16-2: pic16f7x7 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z z z z c c c, dc, z z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1,2 1, 2 1, 2 1, 2 1, 2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc, z z to , pd z to , pd c, dc, z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as i nput and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is m odified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 2003 microchip technology inc. preliminary ds30498b-page 195 pic16f7x7 16.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2 t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b? in register ?f? is ? 0 ?, the next instruction is discarded and a nop is executed instead, making this a 2 t cy instruction.
pic16f7x7 ds30498b-page 196 preliminary ? 2003 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits<10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits, to and pd , are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2003 microchip technology inc. preliminary ds30498b-page 197 pic16f7x7 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2 t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits<10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2 t cy instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
pic16f7x7 ds30498b-page 198 preliminary ? 2003 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register ?f? are moved to a destination dependant upon the status of ?d?. if d = 0 , the destination is w register. if d = 1 , the destination is file register ?f? itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the don?t cares will assemble as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction.
? 2003 microchip technology inc. preliminary ds30498b-page 199 pic16f7x7 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd , is cleared. time-out status bit, to , is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16f7x7 ds30498b-page 200 preliminary ? 2003 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2003 microchip technology inc. preliminary ds30498b-page201 pic16f7x7 17.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc -microid ? -can - powersmart ? -analog 17.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 17.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic16f7x7 ds30498b-page 202 preliminary ? 2003 microchip technology inc. 17.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 17.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 17.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 17.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 17.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 17.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2003 microchip technology inc. preliminary ds30498b-page203 pic16f7x7 17.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 17.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 17.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab inte- grated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 17.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 17.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant.
pic16f7x7 ds30498b-page 204 preliminary ? 2003 microchip technology inc. 17.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 17.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 17.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 17.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 17.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 fam- ily of microcontrollers. picdem 4 is intended to show- case the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. included on the demo board are provisions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for program- ming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a prototyping area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. 17.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion.
? 2003 microchip technology inc. preliminary ds30498b-page205 pic16f7x7 17.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 17.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 17.22 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (inte- grated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 17.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 17.24 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits.
pic16f7x7 ds30498b-page 206 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 207 pic16f7x7 18.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... .-55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr . and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +6.5v voltage on mclr with respect to v ss (note 2) ..............................................................................................0 to +13.5v voltage on ra4 with respect to vss ............................................................................................. ......................0 to +12v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb and porte (combined) (note 3) ....................................................200 ma maximum current sourced by porta, portb and porte (combined) (note 3) ...............................................200 ma maximum current sunk by portc and portd (combined) (note 3) .................................................................200 ma maximum current sourced by portc and portd (combined) (note 3) ............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes at the mclr pin may cause latchup. a series resistor of greater than 1 k ? should be used to pull mclr to v dd , rather than tying the pin directly to v dd . 3: portd and porte are not implemented on the pic16f737/767 devices. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f7x7 ds30498b-page 208 preliminary ? 2003 microchip technology inc. figure 18-1: pic16f7x7 voltage-freq uency graph figure 18-2: PIC16LF7X7 voltage-frequency graph frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v 16 mhz frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 5.0v 3.5v 3.0v 2.5v f max = (12 mhz/v) (v ddappmin - 2.5v) + 4 mhz note 1: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10 mhz.
? 2003 microchip technology inc. preliminary ds30498b-page 209 pic16f7x7 18.1 dc characteristics: pic16f737/747/767/777 (industrial, extended) pic16lf737/747/767/777 (industrial) pic16lf737/747/767/777 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f737/747/767/777 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions v dd supply voltage d001 PIC16LF7X7 2.5 2.2 2.0 ? ? ? 5.5 5.5 5.5 v v v a/d in use, -40c to +85c a/d in use, 0c to +85c a/d not used, -40c to +85c d001 d001a pic16f7x7 4.0 v bor * ? ? 5.5 5.5 v v all configurations bor enabled (note 7) d002* v dr ram data retention voltage (note 1) ?1.5?v d003 v por v dd start voltage to ensure internal power-on reset signal ?v ss ? v see section on power-on reset for details d004* sv dd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details v bor brown-out reset voltage PIC16LF7X7 industrial low voltage d005 borv1:borv0 = 11 na ? na v reserved borv1:borv0 = 10 2.50 2.72 2.94 v borv1:borv0 = 01 3.88 4.22 4.56 v borv1:borv0 = 00 4.18 4.54 4.90 v d005 pic16f7x7 industrial borv1:borv0 = 1x na ? na v not in operating voltage range of device borv1:borv0 = 01 3.88 4.22 4.56 v borv1:borv0 = 00 4.18 4.54 4.90 v legend: shading of rows is to assist in readability of of the table. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from-rail to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f7x7 ds30498b-page 210 preliminary ? 2003 microchip technology inc. 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) PIC16LF7X7 0.1 0.4 a -40c v dd = 2.0v 0.1 0.4 a +25c 0.4 1.5 a +85c PIC16LF7X7 0.3 0.5 a -40c v dd = 3.0v 0.3 0.5 a +25c 0.7 1.7 a +85c all devices 0.6 1.0 a -40c v dd = 5.0v 0.6 1.0 a +25c 1.2 5.0 a +85c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30498b-page 211 pic16f7x7 supply current (i dd ) (2,3) PIC16LF7X7 9 20 a -40c v dd = 2.0v f osc = 32 kh z (lp oscillator) 715 a +25c 715 a +85c PIC16LF7X7 16 30 a -40c v dd = 3.0v 14 25 a +25c 14 25 a +85c all devices 32 40 a -40c v dd = 5.0v 26 35 a +25c 26 35 a +85c PIC16LF7X7 72 95 a -40c v dd = 2.0v f osc = 1 mh z (rc oscillator) (3) 76 90 a +25c 76 90 a +85c PIC16LF7X7 138 175 a -40c v dd = 3.0v 136 170 a +25c 136 170 a +85c all devices 310 380 a -40c v dd = 5.0v 290 360 a +25c 280 360 a +85c PIC16LF7X7 270 315 a -40c v dd = 2.0v f osc = 4 mhz (rc oscillator) (3) 280 310 a +25c 285 310 a +85c PIC16LF7X7 460 610 a -40c v dd = 3.0v 450 600 a +25c 450 600 a +85c all devices 900 1060 a -40c v dd = 5.0v 890 1050 a +25c 890 1050 a +85c 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) (continued) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f7x7 ds30498b-page 212 preliminary ? 2003 microchip technology inc. supply current (i dd ) (2,3) all devices 1.8 2.3 ma -40c v dd = 4.0v f osc = 20 mh z (hs oscillator) 1.6 2.2 ma +25c 1.3 2.2 ma +85c all devices 3.0 4.2 ma -40c v dd = 5.0v 2.5 4.0 ma +25c 2.5 4.0 ma +85c 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) (continued) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30498b-page 213 pic16f7x7 supply current (i dd ) (2,3) PIC16LF7X7 8 20 a -40c v dd = 2.0v f osc = 31.25 khz ( rc_run mode, internal rc oscillator) 715 a +25c 715 a +85c PIC16LF7X7 16 30 a -40c v dd = 3.0v 14 25 a +25c 14 25 a +85c all devices 32 40 a -40c v dd = 5.0v 29 35 a +25c 29 35 a +85c PIC16LF7X7 132 160 a -40c v dd = 2.0v f osc = 1 mhz ( rc_run mode, internal rc oscillator) 126 155 a +25c 126 155 a +85c PIC16LF7X7 260 310 a -40c v dd = 3.0v 230 300 a +25c 230 300 a +85c all devices 560 690 a -40c v dd = 5.0v 500 650 a +25c 500 650 a +85c PIC16LF7X7 310 420 a -40c v dd = 2.0v f osc = 4 mhz ( rc_run mode, internal rc oscillator) 300 410 a +25c 300 410 a +85c PIC16LF7X7 550 650 a -40c v dd = 3.0v 530 620 a +25c 530 620 a +85c all devices 1.2 1.5 ma -40c v dd = 5.0v 1.1 1.4 ma +25c 1.1 1.4 ma +85c 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) (continued) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f7x7 ds30498b-page 214 preliminary ? 2003 microchip technology inc. supply current (i dd ) (2,3) PIC16LF7X7 .950 1.3 ma -40c v dd = 3.0v f osc = 8 mhz ( rc_run mode, internal rc oscillator) .930 1.2 ma +25c .930 1.2 ma +85c all devices 1.8 3.0 ma -40c v dd = 5.0v 1.7 2.8 ma +25c 1.7 2.8 ma +85c PIC16LF7X7 9 13 a -10c v dd = 2.0v f osc = 32 khz ( sec_run mode, timer1 as clock) 914 a +25c 11 16 a +70c PIC16LF7X7 12 34 a -10c v dd = 3.0v 12 31 a +25c 14 28 a +70c all devices 20 72 a -10c v dd = 5.0v 20 65 a +25c 25 59 a +70c 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) (continued) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2003 microchip technology inc. preliminary ds30498b-page 215 pic16f7x7 module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.5 3.8 a -40c v dd = 2.0v 2.2 3.8 a +25c 2.7 4.0 a +85c 2.3 4.6 a -40c v dd = 3.0v 2.7 4.6 a +25c 3.1 4.8 a +85c 3.0 10.0 a -40c v dd = 5.0v 3.3 10.0 a +25c 3.9 13.0 a +85c d022a ( ? i bor ) brown-out reset 17 35 a-40 c to +85 cv dd = 3.0v 47 45 a-40 c to +85 cv dd = 5.0v 00 a-40 c to +85 cv dd = 2.0v v dd = 3.0v v dd = 5.0v boren:borsen = 10 in sleep mode d022b ( ? i lvd ) low-voltage detect 14 25 a-40 c to +85 cv dd = 2.0v 18 35 a-40 c to +85 cv dd = 3.0v 21 45 a-40 c to +85 cv dd = 5.0v d025 ( ? i oscb ) timer1 oscillator 1.7 2.3 a -40c v dd = 2.0v 32 khz on timer1 1.8 2.3 a +25c 2.0 2.3 a +85c 2.2 3.8 a -40c v dd = 3.0v 2.6 3.8 a +25c 2.9 3.8 a +85c 3.0 6.0 a -40c v dd = 5.0v 3.2 6.0 a +25c 3.4 7.0 a +85c d026 ( ? i ad ) a/d converter 0.001 2.0 a-40 c to +85 cv dd = 2.0v a/d on, not converting 0.001 2.0 a-40 c to +85 cv dd = 3.0v 0.003 2.0 a-40 c to +85 cv dd = 5.0v 18.2 dc characteristics: power-down and supply current pic16f7x7 (industrial) PIC16LF7X7 (industrial) (continued) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16f7x7 ds30498b-page 216 preliminary ? 2003 microchip technology inc. 18.3 dc characteristics: internal rc accuracy pic16f7x7 (industrial, extended) PIC16LF7X7 (industrial) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) PIC16LF7X7 -2 1 2 % +25c v dd = 2.7v-3.3v -5 ? 5 % -10c to +85c v dd = 2.7v-3.3v -10 ? 10 % -40c to +85c v dd = 2.7v-3.3v pic16f7x7 -2 1 2 % +25c v dd = 4.5v-5.5v -5 ? 5 % -10c to +85c v dd = 4.5v-5.5v -10 ? 10 % -40c to +85c v dd = 4.5v-5.5v intrc accuracy @ freq = 31 khz (2) PIC16LF7X7 26.562 ? 35.938 khz -40c to +85c v dd = 2.7v-3.3v pic16f7x7 26.562 ? 35.938 khz -40c to +85c v dd = 4.5v-5.5v legend: shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: intrc is used to calibrate intosc.
? 2003 microchip technology inc. preliminary ds30498b-page 217 pic16f7x7 18.4 dc characteristics: pic16f737/747/767/777 (industrial, extended) pic16lf737/747/767/777 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in section 18.1 ?dc characteristics? . param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss ? 0.15 v dd v for entire v dd range d030a v ss ? 0.8v v 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss ? 0.2 v dd v d032 mclr , osc1 (in rc mode) v ss ? 0.2 v dd v (note 1) d033 osc1 (in xt and lp mode) v ss ?0.3v v osc1 (in hs mode) v ss ? 0.3 v dd v v ih input high voltage i/o ports: d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25 v dd + 0.8 v ? v dd v for entire v dd range d041 with schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range d042 mclr 0.8 v dd ?v dd v d042a osc1 (in xt and lp mode) 1.6v ? v dd v osc1 (in hs mode) 0.7 v dd ?v dd v d043 osc1 (in rc mode) 0.9 v dd ?v dd v (note 1) d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports ? ? 1 av ss v pin v dd , pin at high-impedance d061 mclr , re3/t0cki ? ? 5 av ss v pin v dd d063 osc1 ? ? 5 av ss v pin v dd , xt, hs and lp osc configuration * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f7x7 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16f7x7 ds30498b-page 218 preliminary ? 2003 microchip technology inc. v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc osc config) ? ? ? ? 0.6 0.6 v v i ol = 1.6 ma, v dd = 4.5v, -40 c to +125 c i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage d090 i/o ports (note 3) v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc osc config) v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = -1.3 ma, v dd = 4.5v, -40 c to +125 c i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open-drain high voltage ??12vra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ??50pf d102 c b scl, sda in i 2 c mode ? ? 400 pf program flash memory d130 e p endurance 100 1000 ? e/w 25 c at 5v d131 v pr v dd for read 2.0 ? 5.5 v 18.4 dc characteristics: pic16f737/747/767/777 (industrial, extended) pic16lf737/747/767/777 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in section 18.1 ?dc characteristics? . param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f7x7 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2003 microchip technology inc. preliminary ds30498b-page 219 pic16f7x7 table 18-1: comparator specifications table 18-2: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated). param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 - v dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 - ? db 300 300a t resp response time (1)* ? 150 400 600 ns ns pic16f7x7 PIC16LF7X7 301 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated). param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? ? ? 1/4 1/2 lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) d312 vr ur unit resistor value (r)* ? 2 k ? ? 310 t set settling time (1) * ? ? 10 s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?.
pic16f7x7 ds30498b-page 220 preliminary ? 2003 microchip technology inc. figure 18-3: low-voltage detect characteristics table 18-3: low-voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) PIC16LF7X7 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f7x7 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ? max units conditions d420 lvd voltage on v dd transition high to low industrial PIC16LF7X7 lvdl<3:0> = 0000 n/a n/a n/a v reserved lvdl<3:0> = 0001 n/a n/a n/a v reserved lvdl<3:0> = 0010 2.15 2.26 2.37 v lvdl<3:0> = 0011 2.33 2.45 2.58 v lvdl<3:0> = 0100 2.43 2.55 2.68 v lvdl<3:0> = 0101 2.63 2.77 2.91 v lvdl<3:0> = 0110 2.73 2.87 3.01 v lvdl<3:0> = 0111 2.91 3.07 3.22 v lvdl<3:0> = 1000 3.20 3.36 3.53 v lvdl<3:0> = 1001 3.39 3.57 3.75 v lvdl<3:0> = 1010 3.49 3.67 3.85 v lvdl<3:0> = 1011 3.68 3.87 4.07 v lvdl<3:0> = 1100 3.87 4.07 4.28 v lvdl<3:0> = 1101 4.06 4.28 4.49 v lvdl<3:0> = 1110 4.37 4.60 4.82 v d420 lvd voltage on v dd transition high to low industrial pic16f7x7 lvdl<3:0> = 1011 3.68 3.87 4.07 v lvdl<3:0> = 1100 3.87 4.07 4.28 v lvdl<3:0> = 1101 4.06 4.28 4.49 v lvdl<3:0> = 1110 4.37 4.60 4.82 v legend: shading of rows is to assist in readability of the table. ? production tested at t amb = 25c. specifications ov er temperature limits ens ured by characterization.
? 2003 microchip technology inc. preliminary ds30498b-page 221 pic16f7x7 18.5 timing parameter symbology the timing parameter symbols have been created using one of the following formats: figure 18-4: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16f737/767 devices. load condition 1 load condition 2
pic16f7x7 ds30498b-page 222 preliminary ? 2003 microchip technology inc. figure 18-5: external clock timing table 18-4: external clock timing requirements param no. symbol characteristic min typ? max units conditions f osc external clki frequency (note 1) dc ? 1 mhz xt osc mode dc ? 20 mhz hs osc mode dc ? 32 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1t osc external clki period (note 1) 1000 ? ? ns xt osc mode 50 ? ? ns hs osc mode 5??mslp osc mode oscillator period (note 1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 250 ns hs osc mode 5??mslp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3t os l, t os h external clock in (osc1) high or low time 500 ? ? ns xt oscillator 2.5 ? ? ms lp oscillator 15 ? ? ns hs oscillator 4t os r, t os f external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ? ? 15 ns hs oscillator ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
? 2003 microchip technology inc. preliminary ds30498b-page 223 pic16f7x7 figure 18-6: clko and i/o timing table 18-5: clko and i/o timing requirements note: refer to figure 18-4 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ? max units conditions 10* t os h2 ck losc1 to clko ? 75 200 ns (note 1) 11* t os h2 ck hosc1 to clko ? 75 200 ns (note 1) 12* t ck r clko rise time ? 35 100 ns (note 1) 13* t ck f clko fall time ? 35 100 ns (note 1) 14* t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15* t io v2 ck h port in valid before clko t osc + 200 ? ? ns (note 1) 16* t ck h2 io i port in hold after clko 0??ns (note 1) 17* t os h2 io vosc1 (q1 cycle) to port out valid ? 100 255 ns 18* t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) pic16f7x7 100 ? ? ns PIC16LF7X7 200 ? ? ns 19* t io v2 os h port input valid to osc1 (i/o in setup time) 0 ? ? ns 20* t io r port output rise time pic16f7x7 ? 10 40 ns PIC16LF7X7 ? ? 145 ns 21* t io f port output fall time pic16f7x7 ? 10 40 ns PIC16LF7X7 ? ? 145 ns 22??* t inp int pin high or low time t cy ??ns 23??* t rbp rb7:rb4 change int high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are fo r design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode, where clko output is 4 x t osc .
pic16f7x7 ds30498b-page 224 preliminary ? 2003 microchip technology inc. figure 18-7: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 18-8: brown-out reset timing table 18-6: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 18-4 for load conditions. v dd v bor 35 param no. sym characteristic min typ? max units conditions 30 t mc lmclr pulse width (low) 2 ? ? sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.1 s 35 t bor brown-out reset pulse width 100 ? ? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless other wise stated. these parameters are for design guidance only and are not tested.
? 2003 microchip technology inc. preliminary ds30498b-page 225 pic16f7x7 figure 18-9: timer0 and timer1 external clock timings table 18-7: timer0 and timer1 external clock requirements param no. symbol characteristic min typ? max units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 42* t t 0p t0cki period no prescaler t cy + 40 ? ? ns with prescaler greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2, 4, 8 pic16f7x7 15 ? ? ns PIC16LF7X7 25 ? ? ns asynchronous pic16f7x7 30 ? ? ns PIC16LF7X7 50 ? ? ns 46* t t 1l t1cki low time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2, 4, 8 pic16f7x7 15 ? ? ns PIC16LF7X7 25 ? ? ns asynchronous pic16f7x7 30 ? ? ns PIC16LF7X7 50 ? ? ns 47* t t 1p t1cki input period synchronous pic16f7x7 greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) PIC16LF7X7 greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16f7x7 60 ? ? ns PIC16LF7X7 100 ? ? ns f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note: refer to figure 18-4 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki/c1out rc0/t1oso/t1cki tmr0 or tmr1
pic16f7x7 ds30498b-page 226 preliminary ? 2003 microchip technology inc. figure 18-10: capture/compare/pwm timings (ccp1 and ccp2) table 18-8: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 18-4 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2 param no. symbol characteristic min typ? max units conditions 50* t cc l ccp1, ccp2 and ccp3 input low time no prescaler 0.5 t cy + 20 ? ? ns with prescaler pic16f7x7 10 ? ? ns PIC16LF7X7 20 ? ? ns 51* t cc h ccp1, ccp2 and ccp3 input high time no prescaler 0.5 t cy + 20 ? ? ns with prescaler pic16f7x7 10 ? ? ns PIC16LF7X7 20 ? ? ns 52* t cc p ccp1, ccp2 and ccp3 input period 3 t cy + 40 n ? ? ns n = prescale value (1,4 or 16) 53* t cc r ccp1, ccp2 and ccp3 output rise time pic16f7x7 ? 10 25 ns PIC16LF7X7 ? 25 50 ns 54* t cc f ccp1, ccp2 and ccp3 output fall time pic16f7x7 ? 10 25 ns PIC16LF7X7 ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2003 microchip technology inc. preliminary ds30498b-page 227 pic16f7x7 figure 18-11: parallel slave port timing (pic16f747/777 devices only) table 18-9: parallel slave port requirements (pic16f747/777 devices only) param no. symbol characteristic min typ? max units conditions 62 t dt v2 wr h data in valid before wr or cs (setup time) 20 25 ? ? ? ? ns ns extended range only 63* t wr h2 dt iwr or cs to data in invalid (hold time) pic16f7x7 20 ? ? ns PIC16LF7X7 35 ? ? ns 64 t rd l2 dt vrd and cs to data out valid ? ? ? ? 80 90 ns ns extended range only 65 t rd h2 dt ird or cs to data out invalid 10 ? 30 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-4 for load conditions. re2/cs /an7 re0/rd /an5 re1/wr /an6 rd7/psp7:rd0/psp0 62 63 64 65
pic16f7x7 ds30498b-page 228 preliminary ? 2003 microchip technology inc. figure 18-12: spi master mode timing (cke = 0 , smp = 0 ) figure 18-13: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 18-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 18-4 for load conditions.
? 2003 microchip technology inc. preliminary ds30498b-page 229 pic16f7x7 figure 18-14: spi slave mode timing (cke = 0 ) figure 18-15: spi slave mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 18-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 18-4 for load conditions.
pic16f7x7 ds30498b-page 230 preliminary ? 2003 microchip technology inc. table 18-10: spi mode requirements figure 18-16: i 2 c bus start/stop bits timing param no. symbol characteristic min typ? max units conditions 70* t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ??ns 71* t sc h sck input high time (slave mode) t cy + 20 ? ? ns 72* t sc l sck input low time (slave mode) t cy + 20 ? ? ns 73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ? ns 74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ? ns 75* t do r sdo data output rise time pic16f7x7 PIC16LF7X7 ? ? 10 25 25 50 ns ns 76* t do f sdo data output fall time ? 10 25 ns 77* t ss h2 do zss to sdo output high-impedance 10 ? 50 ns 78* t sc r sck output rise time (master mode) pic16f7x7 PIC16LF7X7 ? ? 10 25 25 50 ns ns 79* t sc f sck output fall time (master mode) ? 10 25 ns 80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic16f7x7 PIC16LF7X7 ? ? ? ? 50 145 ns ns 81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy ??ns 82* t ss l2 do v sdo data output valid after ss edge ? ? 50 ns 83* t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 18-4 for load conditions. 91 92 93 scl sda start condition stop condition 90
? 2003 microchip technology inc. preliminary ds30498b-page 231 pic16f7x7 table 18-11: i 2 c bus start/stop bits requirements figure 18-17: i 2 c bus data timing param no. symbol characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? 91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? 92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note: refer to figure 18-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16f7x7 ds30498b-page 232 preliminary ? 2003 microchip technology inc. table 18-12: i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101* t low clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91* t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92* t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2003 microchip technology inc. preliminary ds30498b-page 233 pic16f7x7 figure 18-18: usart synchronous transmission (master/slave) timing table 18-13: usart synchronous transmission requirements figure 18-19: usart synchronous receive (master/slave) timing table 18-14: usart synchronous receive requirements note: refer to figure 18-4 for load conditions. 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 param no. symbol characteristic min typ? max units conditions 120 t ck h2 dt v sync xmit (master & slave) clock high to data out valid pic16f7x7 ? ? 80 ns PIC16LF7X7 ? ? 100 ns 121 t ckrf clock out rise time and fall time (master mode) pic16f7x7 ? ? 45 ns PIC16LF7X7 ? ? 50 ns 122 t dtrf data out rise time and fall time pic16f7x7 ? ? 45 ns PIC16LF7X7 ? ? 50 ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-4 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min typ? max units conditions 125 t dt v2 ck l sync rcv (master & slave) data setup before ck (dt setup time) 15 ? ? ns 126 t ck l2 dtl data hold after ck (dt hold time) 15 ? ? ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f7x7 ds30498b-page 234 preliminary ? 2003 microchip technology inc. table 18-15: a/d converter characteristics: pic16f7x7 (industrial, extended) PIC16LF7X7 (industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution pic16f7x7 ? ? 8 bits bit v ref = v dd = 5.12v, v ss v ain v ref PIC16LF7X7 ? ? 8 bits bit v ref = v dd = 2.2v a02 e abs total absolute error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full-scale error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity (note 3) ? guaranteed ? ? v ss v ain v ref a20 v ref reference voltage 2.5 2.2 ? ? 5.5 5.5 v v -40c to +125c 0c to +125c a25 v ain analog input voltage v ss ? 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ??10.0k ? a40 i ad a/d conversion current (v dd ) pic16f7x7 ? 180 ? a average current consumption when a/d is on (note 1) PIC16LF7X7 ? 90 ? a a50 i ref v ref input current (note 2) n/a ? ? ? 5 500 a a during v ain acquisition. during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
? 2003 microchip technology inc. preliminary ds30498b-page 235 pic16f7x7 figure 18-20: a/d conversion timing table 18-16: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic16f7x7 1.6 ? ? st osc based, v ref 3.0v PIC16LF7X7 2.0 ? ? st osc based, 2.0v v ref 5.5v pic16f7x7 2.0 4.0 6.0 s a/d rc mode PIC16LF7X7 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 9?9t ad 132 t acq acquisition time 5* ? ? s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 12.1 ?a/d acquisition requirements? for minimum conditions.
pic16f7x7 ds30498b-page 236 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 237 pic16f7x7 19.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time.
pic16f7x7 ds30498b-page 238 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 239 pic16f7x7 20.0 packaging information 20.1 package marking information 28-lead pdip (skinny dip) xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic16f737-i/sp 0310017 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic16f767-i/so 0310017 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic16f737 -i/ss 0310017 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn example 16f737 -i/ml 0310017 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic16f7x7 ds30498b-page 240 preliminary ? 2003 microchip technology inc. package marking information (cont?d) example pic16f777-i/p 0310017 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic16f777 -i/pt 0310017 xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn pic16f777 example -i/ml 0310017
? 2003 microchip technology inc. preliminary ds30498b-page 241 pic16f7x7 20.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic
pic16f7x7 ds30498b-page 242 preliminary ? 2003 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
? 2003 microchip technology inc. preliminary ds30498b-page 243 pic16f7x7 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic
pic16f7x7 ds30498b-page 244 preliminary ? 2003 microchip technology inc. 28-lead plastic quad flat no lead package (ml) 6x6 mm body, punch singulated (qfn) lead width *controlling parameter drawing no. c04-114 notes: mold draft angle top dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per side. b .009 12 .011 .014 0.23 12 0.28 0.35 pitch number of pins overall width standoff molded package length overall length molded package width molded package thickness overall height max units dimension limits a2 a1 e1 d d1 e n p a .026 .236 bsc .000 .226 bsc inches .026 bsc min 28 nom max 0.65 .031 .002 0.00 6.00 bsc 5.75 bsc millimeters* .039 min 28 0.65 bsc nom 0.80 0.05 1.00 .008 ref base thickness a3 0.20 ref jedec equivalent: mmo-220 0.85 .033 .0004 0.01 .236 bsc .226 bsc 6.00 bsc 5.75 bsc lead length tie bar width l .020 .024 .030 0.50 0.60 0.75 r .005 .007 .010 0.13 0.17 0.23 tie bar length q .012 .016 .026 0.30 0.40 0.65 chamfer ch .009 .017 .024 0.24 0.42 0.60 e2 d2 exposed pad width exposed pad length .140 .146 .152 3.55 3.70 3.85 .140 .146 .152 3.55 3.70 3.85 d e e1 n 1 2 d1 a a2 exposed metal pads bottom view top view q l r p a1 a3 ch x 45 b d2 e2
? 2003 microchip technology inc. preliminary ds30498b-page 245 pic16f7x7 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
pic16f7x7 ds30498b-page 246 preliminary ? 2003 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic
? 2003 microchip technology inc. preliminary ds30498b-page 247 pic16f7x7 44-lead plastic quad flat no lead package (ml) 8x8 mm body (qfn) contact width *controlling parameter drawing no. c04-103 notes: 1. 2. b .008 .013 .013 0.20 0.33 0.35 pitch number of contacts overall width standoff overall length overall height max units dimension limits a1 d e n p a .000 inches .026 bsc min 44 nom max .002 0 millimeters* .039 min 44 0.65 bsc nom 0.05 1.00 .010 ref base thickness (a3) 0.25 ref 4. 0.90 .035 .001 0.02 .315 8.00 contact length l .014 .016 .019 0.35 0.40 0.48 e2 d2 exposed pad width exposed pad length .246 .268 .274 6.25 6.80 6.95 .246 .268 .274 6.25 6.80 6.95 d2 d a1 (a3) a top view n 1 l e2 bottom view b e 2 pad metal exposed p pin 1 index on exposed pad top marking index on optional pin 1 .031 0.80 detail: contact variants 7.85 8.15 .321 .309 .309 .315 8.00 7.85 .321 8.15 22 11 bsc: basic dimension. theoretically exact value shown without tolerances. jedec equivalent: m0-220 ref: reference dimension, usually without tolerance, for information purposes only. see asme y14.5m see asme y14.5m 3. contact profiles may vary. (profile may vary)
pic16f7x7 ds30498b-page 248 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds30498b-page 249 pic16f7x7 appendix a: revision history revision a (june 2003) this is a new data sheet. however, these devices are similar to the pic16c7x devices found in the pic16c7x data sheet (ds30390) or the pic16f87x devices (ds30292). revision b (november 2003) this revision includes updates to the electrical specifi- cations in section 18.0 ?electrical characteristics? and minor corrections to the data sheet text. appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. table b-1: device differences difference pic16f737 pic16f747 pic16f767 pic16f777 flash program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 368 368 368 368 i/o ports 3 5 3 5 a/d 11 channels, 10 bits 14 channels, 10 bits 11 channels, 10 bits 14 channels, 10 bits parallel slave port no yes no yes interrupt sources 16171617 packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin qfn 44-pin tqfp 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin qfn 44-pin tqfp
pic16f7x7 ds30498b-page 250 preliminary ? 2003 microchip technology inc. appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table c-1. table c-1: conversion considerations characteristic pic16c7x pic16f87x pic16f7x7 pins 28/40 28/40 28/40 timers 3 3 3 interrupts 11 or 12 13 or 14 16 or 17 communication psp, usart, ssp (spi, i 2 c slave) psp, usart, ssp (spi, i 2 c master/slave) psp, ausart, mssp (spi, i 2 c slave) frequency 20 mhz 20 mhz 20 mhz a/d 8-bit 10-bit 10-bit ccp 2 2 3 program memory 4k, 8k eprom 4k, 8k flash (1,000 e/w cycles) 4k, 8k flash (100 e/w cycles) ram 192, 368 bytes 192, 368 bytes 368 bytes eeprom data none 128, 256 bytes none other ? in-circuit debugger, low-voltage programming ?
? 2003 microchip technology inc. preliminary ds30498b-page 251 pic16f7x7 index a a/d a/d converter interrupt, configuring ........................ 155 acquisition requirements ......................................... 156 adresh register..................................................... 154 analog port pins ......................................................... 68 analog-to-digital converter....................................... 151 associated registers ................................................ 160 automatic acquisition time....................................... 157 calculating acquisition time..................................... 156 configuring analog port pins.................................... 158 configuring the module............................................. 155 conversion clock...................................................... 157 conversion requirements ........................................ 235 conversion status (go/done bit) ........................... 154 conversions .............................................................. 159 converter characteristics ......................................... 234 delays ....................................................................... 156 effects of a reset...................................................... 160 internal sampling switch (rss) impedance .............. 156 operation during sleep ............................................ 160 operation in power managed modes ....................... 158 source impedance.................................................... 156 time delays .............................................................. 156 using the ccp trigger.............................................. 160 absolute maximum ratings .............................................. 207 ackstat ......................................................................... 123 adcon0 register go/done bit............................................................ 154 addressable universal synchronous asynchronous receiver transmitter. see usart. adresl register ............................................................. 154 application notes an552 (implementing wake-up on key stroke) ......... 56 an556 (implementing a table read) ......................... 29 an607 (power-up trouble shooting)........................ 173 assembler mpasm assembler................................................... 201 asynchronous reception associated registers ........................................ 141, 143 asynchronous transmission associated registers ................................................ 139 b banking, data memory ....................................................... 15 baud rate generator ........................................................ 119 bf ..................................................................................... 123 block diagrams a/d ............................................................................ 155 analog input model ........................................... 156, 165 baud rate generator................................................ 119 capture mode operation ............................................ 89 comparator i/o operating modes............................. 162 comparator output ................................................... 164 comparator voltage reference ................................ 168 compare ..................................................................... 89 fail-safe clock monitor............................................. 189 in-circuit serial programming connections.............. 192 interrupt logic ........................................................... 184 low-voltage detect (lvd) ........................................ 175 low-voltage detect (lvd) with external input.......... 175 mssp (i 2 c master mode) ......................................... 117 mssp (i 2 c mode) ..................................................... 102 mssp (spi mode) ...................................................... 93 on-chip reset circuit............................................... 172 osc1/clki/ra7 pin................................................... 54 osc2/clko/ra6 pin................................................. 53 pic16f737 and pic16f767 ......................................... 6 pic16f747 and pic16f777 ......................................... 7 portc (peripheral output override) rc<2:0>, rc<7:5> pins..................................... 65 portc (peripheral output override) rc<4:3> pins ..................................................... 65 portd (in i/o port mode) ......................................... 67 portd and porte (parallel slave port).................. 70 porte (in i/o port mode) ......................................... 68 pwm mode................................................................. 91 ra0/an0:ra1/an1 pins............................................. 50 ra2/an2/v ref -/cv ref pin ........................................ 51 ra3/an3/v ref + pin ................................................... 50 ra4/t0cki/c1out pin .............................................. 51 ra5/an4/lvdin/ss /c2out pin................................ 52 rb0/int/an12 pin...................................................... 57 rb1/an10 pin ............................................................ 57 rb2/an8 pin .............................................................. 58 rb3/ccp2/an9 pin.................................................... 59 rb4/an11 pin ............................................................ 60 rb5/an13/ccp3 pin.................................................. 61 rb6/pgc pin.............................................................. 62 rb7/pgd pin.............................................................. 63 recommended mclr circuit................................... 173 system clock.............................................................. 39 timer0/wdt prescaler ............................................... 73 timer1 ........................................................................ 79 timer2 ........................................................................ 85 usart receive ............................................... 140, 142 usart transmit ...................................................... 138 watchdog timer (wdt)............................................ 186 bor. see brown-out reset. brg. see baud rate generator. brgh bit .......................................................................... 135 brown-out reset (bor).................... 169, 172, 173, 179, 180 bus collision during a repeated start condition ............. 130 bus collision during a start condition .............................. 128 bus collision during a stop condition.............................. 131 c c compilers mplab c17.............................................................. 202 mplab c18.............................................................. 202 mplab c30.............................................................. 202 capture/compare/pwm (ccp) .......................................... 87 capture mode............................................................. 89 prescaler ............................................................ 89 ccp pin configuration ......................................... 89, 90 compare mode........................................................... 89 software interrupt mode ..................................... 90 special event trigger output ............................. 90 timer1 mode selection....................................... 90 example pwm frequencies and resolutions ............ 92 interaction of two ccp modules................................ 87 pwm duty cycle ........................................................ 91 pwm mode................................................................. 91 pwm period ............................................................... 91 registers associated with capture, compare and timer1.......................................... 90 registers associated with pwm and timer2 ............. 92
pic16f7x7 ds30498b-page 252 preliminary ? 2003 microchip technology inc. setup for pwm operation ........................................... 92 special event trigger.................................................. 90 timer resources......................................................... 87 ccp1 module...................................................................... 87 ccp2 module...................................................................... 87 ccp3 module...................................................................... 87 ccpr1h register ............................................................... 87 ccpr1l register................................................................ 87 ccpxm<3:0> bits................................................................ 88 ccpxx and ccpxy bits...................................................... 88 clock sources ..................................................................... 37 selection using osccon register ............................ 37 clock switching................................................................... 37 modes (table) .............................................................. 47 transition and the watchdog timer ............................ 38 code examples call of a subroutine in page 1 from page 0................ 29 changing between capture prescalers ...................... 89 changing prescaler assignment from wdt to timer0.................................................... 76 flash program read ................................................... 32 implementing a real-time clock using a timer1 interrupt service ..................................... 82 indirect addressing ..................................................... 30 initializing porta....................................................... 49 loading the sspbuf (sspsr) register .................... 96 reading a 16-bit free running timer......................... 80 saving status and w registers in ram ................... 185 writing a 16-bit free running timer ........................... 80 code protection ........................................................ 169, 192 comparator module .......................................................... 161 analog input connection considerations.................. 165 associated registers ................................................ 165 configuration............................................................. 162 effects of a reset...................................................... 165 interrupts................................................................... 164 operation .................................................................. 163 operation during sleep ............................................ 165 outputs ..................................................................... 163 reference ................................................................. 163 response time ......................................................... 163 comparator specifications ................................................ 219 comparator voltage reference ........................................ 167 associated registers ................................................ 168 computed goto ................................................................ 29 configuration bits.............................................................. 169 conversion considerations ............................................... 250 crystal and ceramic resonators ........................................ 33 d data memory....................................................................... 15 bank select (rp1:rp0 bits) ....................................... 15 general purpose registers......................................... 15 map for pic16f737 and pic16f767 .......................... 16 map for pic16f747 and pic16f777 .......................... 17 special function registers ......................................... 18 dc and ac characteristics graphs and tables ................................................... 237 dc characteristics .................................................... 209, 217 internal rc accuracy ................................................ 216 power-down and supply current .............................. 210 demonstration boards picdem 1................................................................. 204 picdem 17............................................................... 204 picdem 18r pic18c601/801.................................. 205 picdem 2 plus......................................................... 204 picdem 3 pic16c92x............................................. 204 picdem 4................................................................. 204 picdem lin pic16c43x ......................................... 205 picdem usb pic16c7x5 ....................................... 205 picdem.net internet/ethernet .................................. 204 development support ....................................................... 201 device differences............................................................ 249 device overview................................................................... 5 features ....................................................................... 5 direct addressing ............................................................... 30 e electrical characteristics .................................................. 207 errata .................................................................................... 4 evaluation and programming tools.................................. 205 external clock input............................................................ 34 external reference signal ................................................ 163 f fail-safe clock monitor ............................................ 169, 189 firmware instructions ....................................................... 193 fsr register ...................................................................... 30 g general call address support .......................................... 116 i i/o ports.............................................................................. 49 i 2 c mode registers .................................................................. 102 i 2 c mode........................................................................... 102 ack pulse ........................................................ 106, 107 acknowledge sequence timing ............................... 126 baud rate generator ............................................... 119 bus collision repeated start condition ................................. 130 start condition.................................................. 128 stop condition .................................................. 131 clock arbitration ....................................................... 120 effect of a reset ....................................................... 127 general call address support .................................. 116 master mode............................................................. 117 operation.......................................................... 118 repeated start condition timing ..................... 122 master mode reception............................................ 123 master mode start condition .................................... 121 master mode transmission ...................................... 123 multi-master communication, bus collision and arbitration .................................................. 127 multi-master mode .................................................... 127 read/write bit information (r/w bit) ................ 106, 107 serial clock (rc3/sck/scl).................................... 107 slave mode............................................................... 106 addressing........................................................ 106 reception ......................................................... 107 transmission .................................................... 107 sleep operation........................................................ 127 stop condition timing .............................................. 126
? 2003 microchip technology inc. preliminary ds30498b-page 253 pic16f7x7 id locations .............................................................. 169, 192 in-circuit debugger ........................................................... 192 in-circuit serial programming ........................................... 169 in-circuit serial programming (icsp) ............................... 192 indf register ..................................................................... 30 indirect addressing ............................................................. 30 fsr register .............................................................. 15 instruction format ............................................................. 193 instruction set ................................................................... 193 addlw ..................................................................... 195 addwf..................................................................... 195 andlw ..................................................................... 195 andwf..................................................................... 195 bcf........................................................................... 195 bsf ........................................................................... 195 btfsc ...................................................................... 195 btfss ...................................................................... 195 call ......................................................................... 196 clrf......................................................................... 196 clrw ....................................................................... 196 clrwdt................................................................... 196 comf ....................................................................... 196 decf ........................................................................ 196 decfsz.................................................................... 197 goto ....................................................................... 197 incf.......................................................................... 197 incfsz ..................................................................... 197 iorlw ...................................................................... 197 iorwf ...................................................................... 197 movf........................................................................ 198 movlw .................................................................... 198 movwf .................................................................... 198 nop .......................................................................... 198 retfie ..................................................................... 198 retlw ..................................................................... 198 return ................................................................... 199 rlf ........................................................................... 199 rrf........................................................................... 199 sleep ...................................................................... 199 sublw ..................................................................... 199 subwf ..................................................................... 199 swapf ..................................................................... 200 xorlw..................................................................... 200 xorwf..................................................................... 200 summary table......................................................... 194 int interrupt (rb0/int). see interrupt sources. intcon register gie bit......................................................................... 23 int0ie bit.................................................................... 23 int0if bit.................................................................... 23 peie bit....................................................................... 23 rbif bit................................................................. 23, 56 tmr0ie bit.................................................................. 23 inter-integrated circuit. see i 2 c. internal oscillator block ...................................................... 35 intrc modes ............................................................. 36 internal reference signal ................................................. 163 interrupt sources ...................................................... 169, 184 a/d conversion complete ........................................ 155 interrupt-on-change (rb7:rb4) ................................. 56 rb0/int pin, external............................................... 185 tmr0 overflow ......................................................... 185 usart receive/transmit complete ........................ 133 interrupts exiting sleep with ....................................................... 48 synchronous serial port interrupt .............................. 25 interrupts, context saving during..................................... 185 interrupts, enable bits global interrupt enable (gie bit)........................ 23, 184 interrupt-on-change (rb7:rb4) enable (rbie bit).......................................................... 185 peripheral interrupt enable (peie bit)........................ 23 rb0/int enable (int0ie bit)...................................... 23 tmr0 overflow enable (tmr0ie bit)......................... 23 interrupts, flag bits interrupt-on change (rb7:rb4) flag (rbif bit)............................................................ 23 interrupt-on-change (rb7:rb4) flag (rbif bit).............................................. 23, 56, 185 rb0/int flag (int0if bit) .......................................... 23 tmr0 overflow flag (tmr0if bit) ........................... 185 intrc modes adjustment.................................................................. 36 l load conditions................................................................ 221 loading of pc ..................................................................... 29 low-voltage detect .......................................................... 174 characteristics.......................................................... 220 effects of a reset ..................................................... 178 operation.................................................................. 177 current consumption ....................................... 178 reference voltage set point ............................ 178 operation during sleep ............................................ 178 low-voltage detect (lvd) ................................................ 169 lvd. see low-voltage detect. m master clear (mclr ) mclr reset, normal operation............... 172, 179, 180 mclr reset, sleep.................................. 172, 179, 180 operation and esd protection ................................. 173 master synchronous serial port (mssp). see mssp. mclr /v pp /re3 pin .............................................................. 8 mclr /v pp /re3 pin ............................................................ 11 memory organization ......................................................... 15 data memory .............................................................. 15 program memory........................................................ 15 program memory and stack maps ............................. 15 mplab asm30 assembler, linker, librarian ................... 202 mplab icd 2 in-circuit debugger ................................... 203 mplab ice 2000 high-performance universal in-circuit emulator.................................... 203 mplab ice 4000 high-performance universal in-circuit emulator.................................... 203 mplab integrated development environment software .............................................. 201 mplink object linker/mplib object librarian ................ 202 mssp ................................................................................. 93 i 2 c mode. see i 2 c. spi mode.................................................................... 93 spi mode. see spi. mssp mode spi slave mode.......................................................... 99
pic16f7x7 ds30498b-page 254 preliminary ? 2003 microchip technology inc. mssp module clock stretching ........................................................ 112 10-bit slave receive mode (sen = 1) .............. 112 10-bit slave transmit mode .............................. 112 7-bit slave receive mode (sen = 1) ................ 112 7-bit slave transmit mode ................................ 112 clock synchronization and the ckp bit .................... 113 control registers (general) ........................................ 93 operation .................................................................. 106 overview ..................................................................... 93 spi master mode ........................................................ 98 sspbuf...................................................................... 98 sspsr ........................................................................ 98 multi-master mode ............................................................ 127 o opcode field descriptions ................................................ 193 option_reg register intedg bit ................................................................. 22 ps2:ps0 bits .............................................................. 22 psa bit........................................................................ 22 rbpu bit..................................................................... 22 t0cs bit...................................................................... 22 t0se bit ...................................................................... 22 osc1/clki/ra7 pin ....................................................... 8, 11 osc2/clko/ra6 pin ..................................................... 8, 11 oscillator configuration....................................................... 33 ecio ........................................................................... 33 extrc ...................................................................... 179 hs ....................................................................... 33, 179 intio1 ........................................................................ 33 intio2 ........................................................................ 33 intrc ....................................................................... 179 lp........................................................................ 33, 179 rc ......................................................................... 33, 35 rcio ........................................................................... 33 xt ....................................................................... 33, 179 oscillator control register modifying ircf bits .................................................... 39 clock transition sequence ................................. 40 oscillator delay upon power-up, wake-up and clock switching.................................................... 40 oscillator start-up timer (ost) ................................ 169, 173 oscillator switching............................................................. 37 p packaging ......................................................................... 239 marking ..................................................................... 239 paging, program memory ................................................... 29 parallel slave port associated registers .................................................. 71 parallel slave port (psp) .............................................. 67, 70 re0/rd /an5 pin......................................................... 68 re1/wr /an6 pin ........................................................ 68 re2/cs /an7 pin......................................................... 68 select (pspmode bit) ......................................... 67, 68 pcl register....................................................................... 29 pclath register................................................................ 29 pcon register ................................................................. 178 por bit ....................................................................... 28 peripheral interrupt (peie bit)............................................. 23 pickit 1 flash starter kit................................................... 205 picstart plus development programmer ..................... 203 pinout descriptions pic16f737/pic16f767 .......................................... 8?10 pic16f747/pic16f777 ........................................ 11?14 pmadr register ................................................................ 31 pop .................................................................................... 29 por. see power-on reset. porta ........................................................................... 8, 11 associated registers .................................................. 55 porta register ......................................................... 49 trisa register........................................................... 49 porta register ................................................................. 49 portb ........................................................................... 9, 12 associated registers .................................................. 64 portb register ......................................................... 56 pull-up enable (rbpu bit).......................................... 22 rb0/int edge select (intedg bit) ........................... 22 rb0/int pin, external............................................... 185 rb7:rb4 interrupt-on-change ................................. 185 rb7:rb4 interrupt-on-change enable (rbie bit).......................................................... 185 rb7:rb4 interrupt-on-change flag (rbif bit).............................................. 23, 56, 185 trisb register........................................................... 56 portb register ................................................................. 56 portc ......................................................................... 10, 13 associated registers .................................................. 66 portc register......................................................... 65 rc3/sck/scl pin .................................................... 107 rc6/tx/ck pin......................................................... 134 rc7/rx/dt pin................................................. 134, 135 trisc register................................................... 65, 133 portc register................................................................. 65 portd ............................................................................... 14 associated registers .................................................. 67 parallel slave port (psp) function............................. 67 portd register......................................................... 67 trisd register........................................................... 67 portd register................................................................. 67 porte ............................................................................... 14 analog port pins ......................................................... 68 associated registers .................................................. 68 input buffer full status (ibf bit) ................................. 69 input buffer overflow (ibov bit)................................. 69 porte register ......................................................... 68 psp mode select (pspmode bit) ....................... 67, 68 re0/rd /an5 pin ........................................................ 68 re1/wr /an6 pin........................................................ 68 re2/cs /an7 pin......................................................... 68 trise register........................................................... 68 porte register ................................................................. 68 postscaler, wdt assignment (psa bit) ................................................. 22 rate select (ps2:ps0 bits) ........................................ 22 power managed modes...................................................... 41 rc_run..................................................................... 41 sec_run................................................................... 42 sec_run/rc_run to primary clock source........... 43 power-down mode. see sleep. power-on reset (por)..................... 169, 172, 173, 179, 180 por status (por bit) ................................................ 28 power control (pcon) register............................... 178 power-down (pd bit) ................................................ 172 time-out (to bit) ................................................ 21, 172
? 2003 microchip technology inc. preliminary ds30498b-page 255 pic16f7x7 power-up timer (pwrt) .......................................... 169, 173 pr2 register....................................................................... 85 prescaler, timer0 assignment (psa bit) ................................................. 22 rate select (ps2:ps0 bits) ........................................ 22 pro mate ii universal device programmer ................... 203 program counter reset conditions....................................................... 179 program memory flash associated registers .......................................... 32 interrupt vector ........................................................... 15 memory and stack maps ............................................ 15 operation during code-protect .................................. 32 organization................................................................ 15 paging......................................................................... 29 pmadr register......................................................... 31 pmadrh register ...................................................... 31 reading....................................................................... 31 reading flash............................................................. 32 reading, pmadr register ......................................... 31 reading, pmadrh register....................................... 31 reading, pmcon1 register....................................... 31 reading, pmdata register ....................................... 31 reading, pmdath register ....................................... 31 reset vector ............................................................... 15 program verification ......................................................... 192 programming, device instructions .................................... 193 push .................................................................................. 29 r ra0/an0 pin ................................................................... 8, 11 ra1/an1 pin ................................................................... 8, 11 ra2/an2/v ref -/cv ref pin............................................. 8, 11 ra3/an3/v ref + pin........................................................ 8, 11 ra4/t0cki/c1out pin .................................................. 8, 11 ra5/an4/lvdin/ss /c2out pin .................................... 8, 11 ram. see data memory. rb0/int/an12 pin .......................................................... 9, 12 rb1/an10 pin ................................................................. 9, 12 rb2/an8 pin ................................................................... 9, 12 rb3/ccp2/an9 pin ........................................................ 9, 12 rb4/an11 pin ................................................................. 9, 12 rb5/an13/ccp3 pin ...................................................... 9, 12 rb6/pgc pin .................................................................. 9, 12 rb7/pgd pin .................................................................. 9, 12 rc0/t1oso/t1cki pin ................................................ 10, 13 rc1/t1osi/ccp2 pin................................................... 10, 13 rc2/ccp1 pin .............................................................. 10, 13 rc3/sck/scl pin ........................................................ 10, 13 rc4/sdi/sda pin ......................................................... 10, 13 rc5/sdo pin ................................................................ 10, 13 rc6/tx/ck pin ............................................................. 10, 13 rc7/rx/dt pin ............................................................. 10, 13 rcio oscillator ................................................................... 35 rcsta register adden bit ................................................................ 134 cren bit................................................................... 134 ferr bit ................................................................... 134 oerr bit .................................................................. 134 rx9 bit...................................................................... 134 rx9d bit ................................................................... 134 spen bit ........................................................... 133, 134 sren bit................................................................... 134 rd0/psp0 pin .................................................................... 14 rd1/psp1 pin .................................................................... 14 rd2/psp2 pin .................................................................... 14 rd3/psp3 pin .................................................................... 14 rd4/psp4 pin .................................................................... 14 rd5/psp5 pin .................................................................... 14 rd6/psp6 pin .................................................................... 14 rd7/psp7 pin .................................................................... 14 re0/rd /an5 pin ................................................................ 14 re1/wr /an6 pin................................................................ 14 re2/cs /an7 pin................................................................. 14 read-modify-write operations ......................................... 193 register file........................................................................ 15 registers adcon0 (a/d control 0).......................................... 152 adcon1 (a/d control 1).......................................... 153 ccpxcon (ccpx control)......................................... 88 cmcon (comparator control) ................................. 161 cvrcon (voltage reference control) .................... 167 initialization conditions (table).......................... 180?181 intcon (interrupt control) ........................................ 23 lvdcon (lvd control)............................................ 176 option_reg ...................................................... 22, 75 osccon (oscillator control)..................................... 38 osctune (oscillator tuning).................................... 36 pcon (power control) ............................................... 28 pie1 (peripheral interrupt enable 1) .......................... 24 pie2 (peripheral interrupt enable 2) .......................... 26 pir1 (peripheral interrupt request 1) ........................ 25 pir2 (peripheral interrupt request 2) ........................ 27 pmcon1 (program memory control 1) ..................... 31 rcsta (receive status and control) ...................... 134 special function, summary.................................. 18?20 sspcon (mssp control) register 1 (i 2 c mode) ........................................................ 104 sspcon (mssp control) register 1 (spi mode) ......................................................... 95 sspcon2 (mssp control) register 2 (i 2 c mode) ........................................................ 105 sspstat (mssp status), i 2 c mode ....................... 103 sspstat (mssp status), spi mode......................... 94 status ......................................................................... 21 t1con (timer1 control) ............................................ 78 t2con (timer2 control) ............................................ 86 trise ......................................................................... 69 txsta (transmit status and control)...................... 133 wdtcon (wdt control) ......................................... 187 reset ........................................................................ 169, 172 brown-out reset (bor). see brown-out reset (bor). mclr reset. see mclr . power-on reset (por). see power-on reset (por). reset conditions for all registers.................... 180, 181 reset conditions for pcon register ....................... 179 reset conditions for program counter .................... 179 reset conditions for status register ....................... 179 wdt reset. see watchdog timer (wdt). revision history................................................................ 249 s sci. see usart. sck .................................................................................... 93 sdi...................................................................................... 93 sdo .................................................................................... 93 serial clock, sck ............................................................... 93 serial communication interface. see usart.
pic16f7x7 ds30498b-page 256 preliminary ? 2003 microchip technology inc. serial data in, sdi .............................................................. 93 serial data out, sdo.......................................................... 93 serial peripheral interface. see spi. slave select synchronization.............................................. 99 slave select, ss ................................................................. 93 sleep ................................................................. 169, 172, 190 software simulator (mplab sim)..................................... 202 software simulator (mplab sim30)................................. 202 special features of the cpu............................................. 169 special function registers ..................................... 18, 18?20 spi mode ...................................................................... 93, 99 associated registers ................................................ 101 bus mode compatibility ............................................ 101 effects of a reset...................................................... 101 enabling spi i/o ......................................................... 97 master mode ............................................................... 98 master/slave connection ............................................ 97 serial clock................................................................. 93 serial data in .............................................................. 93 serial data out ........................................................... 93 slave select ................................................................ 93 slave select synchronization ..................................... 99 sleep operation ........................................................ 101 spi clock .................................................................... 98 typical connection ..................................................... 97 ss ....................................................................................... 93 ssp spi master/slave connection ..................................... 97 sspif bit............................................................................. 25 sspov.............................................................................. 123 sspstat register r/w bit .............................................................. 106, 107 stack ................................................................................... 29 overflows .................................................................... 29 underflow .................................................................... 29 status register c bit ............................................................................ 21 dc bit.......................................................................... 21 irp bit......................................................................... 21 pd bit .................................................................. 21, 172 to bit .................................................................. 21, 172 z bit............................................................................. 21 synchronous master reception associated registers ................................................ 146 synchronous master transmission associated registers ................................................ 145 synchronous serial port interrupt flag bit (sspif) ............ 25 synchronous slave reception associated registers ................................................ 149 synchronous slave transmission associated registers ................................................ 148 t t1ckps0 bit ....................................................................... 78 t1ckps1 bit ....................................................................... 78 t1oscen bit ...................................................................... 78 t1sync bit......................................................................... 78 t2ckps0 bit ....................................................................... 86 t2ckps1 bit ....................................................................... 86 t ad .................................................................................... 157 time-out sequence........................................................... 178 timer0................................................................................. 73 associated registers .................................................. 76 clock source edge select (t0se bit) ........................ 22 clock source select (t0cs bit).................................. 22 external clock............................................................. 74 interrupt ...................................................................... 73 operation .................................................................... 73 overflow enable (tmr0ie bit).................................... 23 overflow flag (tmr0if bit) ...................................... 185 overflow interrupt ..................................................... 185 prescaler .................................................................... 74 t0cki ......................................................................... 74 timer1................................................................................. 77 associated registers .................................................. 83 asynchronous counter mode ..................................... 80 reading and writing ........................................... 80 capacitor selection..................................................... 81 counter operation ...................................................... 79 operation .................................................................... 77 operation in synchronized counter mode.................. 79 operation in timer mode ............................................ 79 oscillator..................................................................... 81 oscillator layout considerations ................................ 81 prescaler .................................................................... 82 resetting timer1 register pair................................... 82 resetting timer1 using a ccp trigger output .......... 81 use as a real-time clock .......................................... 82 timer2................................................................................. 85 associated registers .................................................. 86 output ......................................................................... 85 postscaler................................................................... 85 prescaler .................................................................... 85 prescaler and postscaler............................................ 85 timing diagrams a/d conversion......................................................... 235 acknowledge sequence ........................................... 126 asynchronous master transmission......................... 139 asynchronous master transmission (back to back) .................................................. 139 asynchronous reception.......................................... 140 asynchronous reception with address byte first ............................................ 143 asynchronous reception with address detect ................................................. 143 baud rate generator with clock arbitration............. 120 brg reset due to sda arbitration during start condition.................................................. 129 brown-out reset ....................................................... 224 bus collision during a repeated start condition (case 1)............................................ 130 bus collision during a repeated start condition (case 2)............................................ 130 bus collision during a stop condition (case 1)............................................................ 131 bus collision during a stop condition (case 2)............................................................ 131 bus collision during start condition (scl = 0) .......................................................... 129 bus collision during start condition (sda only) ....................................................... 128 bus collision for transmit and acknowledge ........... 127 capture/compare/pwm (ccp1 and ccp2)............. 226
? 2003 microchip technology inc. preliminary ds30498b-page 257 pic16f7x7 clko and i/o ........................................................... 223 clock synchronization .............................................. 113 external clock........................................................... 222 fail-safe clock monitor............................................. 189 first start bit ............................................................. 121 i 2 c bus data ............................................................. 231 i 2 c bus start/stop bits.............................................. 230 i 2 c master mode (reception, 7-bit address) ................................................... 125 i 2 c master mode (transmission, 7 or 10-bit address) .......................................... 124 i 2 c slave mode (transmission, 10-bit address) ................................................. 111 i 2 c slave mode (transmission, 7-bit address) ................................................... 109 i 2 c slave mode with sen = 0 (reception, 10-bit address) ................................................. 110 i 2 c slave mode with sen = 0 (reception, 7-bit address) ................................................... 108 i 2 c slave mode with sen = 1 (reception, 10-bit address) ................................................. 115 i 2 c slave mode with sen = 1 (reception, 7-bit address) ................................................... 114 low-voltage detect................................................... 177 lp clock to primary system clock after reset (ec, rc, intrc) ...................................... 46 lp clock to primary system clock after reset (hs, xt, lp) ............................................. 45 parallel slave port .................................................... 227 parallel slave port read............................................. 71 parallel slave port write ............................................. 71 power-up timer ........................................................ 224 pwm output ............................................................... 91 repeat start condition.............................................. 122 reset......................................................................... 224 slave mode general call address sequence (7 or 10-bit address mode) ............................... 116 slave synchronization ................................................ 99 slow rise time (mclr tied to v dd through rc network) ....................................... 183 spi master mode (cke = 0, smp = 0) ..................... 228 spi master mode (cke = 1, smp = 1) ..................... 228 spi mode (master mode)............................................ 98 spi mode (slave mode with cke = 0) ...................... 100 spi mode (slave mode with cke = 1) ...................... 100 spi slave mode (cke = 0) ....................................... 229 spi slave mode (cke = 1) ....................................... 229 start-up timer ........................................................... 224 stop condition receive or transmit mode ............... 126 switching to sec_run mode .................................... 42 synchronous reception (master mode, sren) ...................................... 147 synchronous transmission....................................... 145 synchronous transmission (through txen) ........... 145 time-out sequence on power-up (mclr tied to v dd through pull-up resistor) ............. 182 time-out sequence on power-up (mclr tied to v dd through rc network): case 1 ...... 182 time-out sequence on power-up (mclr tied to v dd through rc network): case 2 ...... 182 timer0 ...................................................................... 225 timer1 ...................................................................... 225 timer1 incrementing edge ......................................... 79 transition between sec_run/rc_run and primary clock .............................................. 44 two-speed start-up ................................................. 188 usart synchronous receive (master/slave) .................................................. 233 usart synchronous transmission (master/slave) .................................................. 233 wake-up from sleep via interrupt............................. 191 watchdog timer ....................................................... 224 xt, hs, lp, ec, extrc to rc_run mode .............. 41 timing parameter symbology .......................................... 221 timing requirements capture/compare/pwm (ccp1 and ccp2)............. 226 clko and i/o ........................................................... 223 external clock .......................................................... 222 i 2 c bus data............................................................. 232 i 2 c bus start/stop bits ............................................. 231 parallel slave port .................................................... 227 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset........................................ 224 spi mode.................................................................. 230 timer0 and timer1 external clock ........................... 225 usart synchronous receive ................................. 233 usart synchronous transmission ......................... 233 tmr1cs bit........................................................................ 78 tmr1on bit ....................................................................... 78 tmr2on bit ....................................................................... 86 toutps<3:0> bits ............................................................. 86 trisa register................................................................... 49 trisb register................................................................... 56 trisc register................................................................... 65 trisd register................................................................... 67 trise register................................................................... 68 ibf bit......................................................................... 69 ibov bit...................................................................... 69 pspmode bit ...................................................... 67, 68 two-speed clock start-up mode...................................... 188 two-speed start-up.......................................................... 169 txsta register brgh bit .................................................................. 133 csrc bit .................................................................. 133 trmt bit .................................................................. 133 tx9 bit...................................................................... 133 tx9d bit ................................................................... 133 txen bit................................................................... 133 u usart ............................................................................. 133 address detect enable (adden bit)........................ 134 asynchronous mode................................................. 138 asynchronous receive (9-bit mode) ........................ 142 asynchronous receive with address detect. see asynchronous receive (9-bit mode). asynchronous receiver............................................ 140 asynchronous reception.......................................... 141 asynchronous transmitter........................................ 138
pic16f7x7 ds30498b-page 258 preliminary ? 2003 microchip technology inc. baud rate generator (brg)..................................... 135 associated registers ........................................ 135 baud rate formula........................................... 135 baud rates, asynchronous mode (brgh = 0) ............................................... 136 baud rates, asynchronous mode (brgh = 1) ............................................... 136 high baud rate select (brgh bit)................... 133 intrc baud rates, asynchronous mode (brgh = 0) ............................................... 137 intrc baud rates, asynchronous mode (brgh = 1) ............................................... 137 sampling ........................................................... 135 clock source select (csrc bit) ............................... 133 continuous receive enable (cren bit) ................... 134 framing error (ferr bit) ......................................... 134 overrun error (oerr bit) ......................................... 134 receive data, 9th bit (rx9d bit) .............................. 134 receive enable, 9-bit (rx9 bit) ................................ 134 serial port enable (spen bit)........................... 133, 134 single receive enable (sren bit) ........................... 134 synchronous master mode ....................................... 144 synchronous master reception ................................ 146 synchronous master transmission........................... 144 synchronous slave mode ......................................... 148 synchronous slave reception .................................. 149 synchronous slave transmit .................................... 148 transmit data, 9th bit (tx9d)................................... 133 transmit enable (txen bit)...................................... 133 transmit enable, nine-bit (tx9 bit) .......................... 133 transmit shift register status (trmt bit)................ 133 v voltage reference specifications..................................... 219 w wake-up from sleep ................................................. 169, 190 interrupts .......................................................... 179, 180 mclr reset ............................................................. 180 wdt reset ............................................................... 180 wake-up using interrupts ................................................. 191 watchdog timer (wdt)............................................ 169, 186 associated registers ................................................ 187 wdt reset, normal operation................. 172, 179, 180 wdt reset, sleep .................................... 172, 179, 180 wcol ............................................................... 121, 123, 126 wcol status flag............................................................ 121 www, on-line support .................... ................................... 4
? 2003 microchip technology inc. preliminary ds30498b-page 259 pic16f7x7 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
pic16f7x7 ds30498b-page 260 preliminary ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30498b pic16f7x7 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. preliminary ds30498b-page 261 pic16f7x7 pic16f7x7 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx xxx pattern package temperature range device device pic16f7x7 (1) , pic16f7x7t (1) ; v dd range 4.0v to 5.5v PIC16LF7X7 (1) , PIC16LF7X7t (1) ; v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) e=-40 c to +125 c (extended) package ml = qfn (micro lead frame) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f777-i/p 301 = industrial temp., pdip package, normal v dd limits, qtp pattern #301. b) pic16lf767-i/so = industrial temp., soic package, extended v dd limits. c) pic16f747-e/p = extended temp., pdip package, normal v dd limits. note 1: f = cmos flash lf = low-power cmos flash 2: t = in tape and reel ? soic, ssop, tqfp packages only.
ds30498b-page 262 preliminary ? 2003 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice

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